Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made that the instant application is a continuation of US patent application 17991560 filed on 11/21/2022. US patent application 17991560 is a divisional of US patent application 16523453 filed on 07/26/2019. US Patent application 16523453 has a provisional 62736565 filed on 09/26/2018.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-3, 11, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20170323824 A1 – hereinafter Chang).
Regarding Claim 1, Chang teaches an apparatus (see the entire document; Fig. 7 along with Figs. 1-6; specifically, ([0009] - [0021]), and as cited below), comprising:
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Chang – annotated Fig. 7
a functional transistor (transistor containing fin 14; annotated Fig. 7) that includes:
a source/drain (32 – [0013]) disposed in an active region (14 – [0009]);
a first gate (46 – see also Fig. 3) disposed over the active region (14) in a first type of cross-sectional side view defined by a vertical direction and a first horizontal direction (seen in Fig. 7); and
a first gate spacer structure (58A – annotated Fig. 7, [0020]) disposed between the first gate (46) and the source/drain (32) in the first horizontal direction in the first type of cross-sectional side view, wherein the first gate spacer structure includes a first air gap (60A – [0020]); and
a non-functional transistor (transistor containing 16) that includes:
a second gate (50 – [0021] - see Fig. 3) disposed over an electrically-insulative structure (16 – STI in [0009]) in the first type of cross-sectional side view (annotated Fig. 7); and
a second gate spacer structure (58B) disposed adjacent to the second gate (50) in the first horizontal direction in the first type of cross-sectional side view (annotated Fig. 7), wherein the second gate spacer structure (58B) includes a second air gap (60B) having a different size than the first air gap in the vertical direction or in the first horizontal direction in the first type of cross-sectional side view (annotated Fig. 7 shows airgap 60B is higher than airgap 60A, see also [0020]).
Regarding Claim 2, Chang teaches the apparatus of claim 1, wherein the non-functional transistor does not conduct electricity (since it has no active area as layer 16 is an insulation – see [0009]).
Regarding Claim 3, Chang teaches the apparatus of claim 1, wherein the non-functional transistor lacks a source/drain (Fig. 7 shows no source/drain).
Regarding Claim 11, Chang teaches an apparatus (see the entire document; Fig. 7 along with Figs. 1-6; specifically, ([0009] - [0021]), and as cited below), comprising:
a functional transistor (transistor containing fin 14; annotated Fig. 7 above in the rejection of claim 1) that is a part of an electronic circuit (semiconductor device in [0009]), the functional transistor including:
a source/drain (32 – [0013]) at least partially surrounded by an active region (14 – [0009]) in a first type of cross-sectional side view defined by a vertical direction and a first horizontal direction (Fig. 7);
a first gate (46 – see also Fig. 3) disposed over the active region (14); and
a first gate spacer structure (58A – annotated Fig. 7, [0020]) disposed between the first gate (46) and the source/drain (32) in the first horizontal direction in the first type of cross-sectional side view, wherein the first gate spacer structure (58A) includes a first air spacer component (60A – [0020]); and
a dummy transistor (transistor containing 16) that is not a part of any electronic circuit (as there is no active region), the dummy transistor including:
a second gate (50 – [0021] - see Fig. 3) disposed over an electrically-insulative structure (16 – STI in [0009]) in the first type of cross-sectional side view (Fig. 7); and
a second gate spacer structure (58B) disposed adjacent to the second gate (50) in the first horizontal direction in the first type of cross-sectional side view, wherein the second gate spacer structure (58B) includes a second air spacer component (60B) having a different geometric profile than the first air spacer component in the first type of cross-sectional side view (annotated Fig. 7 shows airgap 60B is higher than airgap 60A, see also [0020]).
Regarding Claim 17, Chang teaches the apparatus of claim 11, wherein the dummy transistor is free of having any source/drain components (since it has no active area as layer 16 is an insulation – see [0009]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Lee et al. (US 20150214235 A1 - hereinafter Lee).
Regarding Claim 4, Chang teaches claim 1 from which claim 4 depends. While Chang teaches air gap 60 could be higher than, even with or lower than the top surface of the gate structures, Chang does not expressly disclose wherein the first air gap is larger than the second air gap.
In a related art, Lee teaches in [0051] “The vertical dimension (with respect to substrate surface) and row dimension (along x-axis) of the air gaps can vary to meet the particular requirements (e.g., suitable isolation parameters) of a given implementation”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the first air gap is larger than the second air gap as taught by Lee into Chang.
An ordinary artisan would have been motivated to integrate Lee structure into Chang structure in the manner set forth above for, at least, this integration will enable one skilled in the art to airgaps of different dimensions to meet particular requirements of a given implementation – Lee – [0051].
Regarding Claim 5, the combination of Chang and Lee teaches the apparatus of claim 4, wherein the first air gap is larger than the second air gap in both the vertical direction and in the first horizontal direction (Lee in [0051] teaches “row dimension (along x-axis) of the air gaps can vary to meet the particular requirements (e.g., suitable isolation parameters) of a given implementation”).
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Lee and in further view of Zang et al. (US 9831346 B1 – hereinafter Zang).
Regarding Claim 18, Chang teaches an apparatus (see the entire document; Fig. 7 along with Figs. 1-6; specifically, ([0009] - [0021]), and as cited below), comprising:
a functional transistor (transistor containing fin 14; annotated Fig. 7), wherein the functional transistor includes:
a source/drain (32 – [0013]) disposed in an active region (14 – [0009]);
a first gate (46 – see also Fig. 3) disposed over the active region (14) in a first type of cross-sectional side view defined by a vertical direction and a first horizontal direction (Fig. 7); and
a first air spacer (60A – [0020]) disposed between the first gate (46) and the source/drain (32) in the first horizontal direction in the first type of cross-sectional side view (Fig. 7); and
a non-functional transistor (transistor containing 16) that is not a part of the electronic memory circuit (as there is not active region), wherein the non-functional transistor does not conduct electricity (since 16 is an isolation), but includes:
a second gate (50 – [0021] - see Fig. 3) disposed over a dielectric isolation structure (16 – STI in [0009]) in the first type of cross-sectional side view (Fig. 7); and
a second air spacer (60B) disposed adjacent to the second gate (50) in the first horizontal direction in the first type of cross-sectional side view.
But Chang as applied above does not expressly disclose the functional transistor that is a part of an electronic memory circuit and wherein the first air spacer is taller than the second air spacer in the vertical direction and wider than the second air spacer in the first horizontal direction in the first type of cross-sectional side view.
In a related art, Lee teaches in [0051] “The vertical dimension (with respect to substrate surface) and row dimension (along x-axis) of the air gaps can vary to meet the particular requirements (e.g., suitable isolation parameters) of a given implementation”.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the first air spacer is taller than the second air spacer in the vertical direction and wider than the second air spacer in the first horizontal direction in the first type of cross-sectional side view as taught by Lee into Chang.
An ordinary artisan would have been motivated to integrate Lee structure into Chang structure in the manner set forth above for, at least, this integration will enable one skilled in the art to airgaps of different dimensions to meet particular requirements of a given implementation – Lee – [0051].
But the combination of Chang and Lee does not expressly disclose the functional transistor that is a part of an electronic memory circuit.
In a related art, Zang teaches a FinFet transistor having air gaps (C1 L62 – C2L6) implemented in a memory cell (C10 L33-39).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the functional transistor that is a part of an electronic memory circuit as taught by Zand into the combination of Chang and Lee to take advantage fabricating a functional memory cell.
Allowable Subject Matter
Claims 6-10, 12-16, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 6: The apparatus of claim 1, wherein:
the first gate spacer structure includes a first dielectric layer;
a first portion of the first dielectric layer is located directly below the first air gap in the vertical direction in the first type of cross-sectional side view;
the second gate spacer structure includes a second dielectric layer;
a first portion of the second dielectric layer is located directly below the first air gap in the vertical direction in the first type of cross-sectional side view; and
an upper surface of the first portion of the first dielectric layer is more elevated in the vertical direction than an upper surface of the first portion of the second dielectric layer in the first type of cross-sectional side view.
Claims 7-10 depend from claim 6.
Regarding claim 12: The apparatus of claim 11, wherein the second gate includes at least one extra dielectric layer compared to the first gate spacer structure.
Claim 13 depend from claim 12.
Regarding claim 14: The apparatus of claim 11, wherein:
the first air spacer component has a first upper boundary and a first lower boundary;
the second air spacer component has a second upper boundary and a second lower boundary;
the first upper boundary is less elevated than an upper surface of the first gate in the vertical direction in the first type of cross-sectional side view;
the first lower boundary is more elevated than a lower surface of the first gate in the vertical direction in the first type of cross-sectional side view;
the second upper boundary is less elevated than an upper surface of the second gate in the vertical direction in the first type of cross-sectional side view; and
the second lower boundary is more elevated than a lower surface of the second gate in the vertical direction in the first type of cross-sectional side view.
Claims 15-16 depend from claim 14.
Regarding claim 19: The apparatus of claim 18, wherein:
a bottom surface of the first air spacer is defined by a first type of dielectric material;
a bottom surface of the second air spacer is defined by a second type of dielectric material; and
the first type of dielectric material and the second type of dielectric material have different material compositions.
Claim 20 depend from claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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