DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species E, claims 1-2, 4-15, and 17-20 in the reply filed on 6/28/2026 is acknowledged.
Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species e.g., J, due to the claims having within their scope an invention with the first corner die corner side to located inside the first semiconductor die first corner side, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/28/2026.
Claim 19 is drawn to nonelected Species J in the alternative. When replying, Applicant is required to amend claim 19 to remove the nonelected “…or the first corner die corner side is located inside the first semiconductor die first corner side and a distance between the first corner die corner side and the first semiconductor die first corner side is less than 1000 µm”.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh (US 2022/0208717).
(Re Claim 1) Oh teaches a semiconductor module comprising:
a first semiconductor die (10; Fig. 7B);
a second semiconductor die (upper left 20e; Fig. 7B) on the first semiconductor die; and
a first corner die (bottom left 20e; Fig. 7B) adjacent to the second semiconductor die on the first semiconductor die and including a first corner die first side (top side; Fig. 7B), a first corner die second side (bottom side; Fig. 7B) and a first corner die corner side (left side; Fig. 7B) connecting the first corner die first side and the first corner die second side, wherein the first corner die is located over a side (left side; Fig. 7B) of the first semiconductor die.
(Re Claim 2) Oh teaches the semiconductor module of claim 1, wherein the side of the first semiconductor die comprises a first semiconductor die first side (top side; Fig. 7B), a first semiconductor die second side (bottom side; Fig. 7B) and a first semiconductor die first corner side (left side; Fig. 7B) connecting the first semiconductor die first side and the first semiconductor die second side, and at least one of:
the first corner die first side is outside the first semiconductor die first side (Fig. 7B);
the first corner die second side is outside the first semiconductor die second side (Fig. 7B); or the first corner die corner side is outside the first semiconductor die first corner side (Fig. 7B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, and 8-13 rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2022/0189907), Yu et al. (US 2014/0042643), Wilkerson et al. (US 2022/0392882) of record, Fuergut et al. (US 2022/0148934), and Wang et al. (US 2022/0310501)
(Re Claim 1) Nam teaches a semiconductor module comprising:
a second semiconductor die (222; Fig. 4A); and
a first corner die (bottom left 221; Fig. 4A) adjacent to the second semiconductor die on the first semiconductor die.
Nam has not been shown to explicitly teach a first semiconductor die; the second semiconductor die is on the first semiconductor die; and the first corner die includes a first corner die first side, a first corner die second side and a first corner die corner side connecting the first corner die first side and the first corner die second side,
wherein the first corner die is located over a side of the first semiconductor die.
Yu teaches forming a second semiconductor die (301; Fig. 3B) surrounded by four corner dies (303; Fig. 3B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize four corner dies (each 221; Fig. 4A) of Nam surrounding the second semiconductor die, as arranged in Yu, instead of the six corner dies, to reduce the number of die attachment steps when forming the semiconductor module.
Nam teaches that a base (101; Fig. 1D) having a plurality of semiconductor dies placed on it (¶25) may be either an interposer or a semiconductor die (¶26).
Wilkerson teaches forming a first semiconductor die (100; Fig. 5 and 7); and a first corner die (200; Fig. 5), wherein the first corner die is located over a side (left side; Fig. 5) of the first semiconductor die.
A PHOSITA would find it obvious to form the interposer 101a of Nam as the first semiconductor die, as Nam teaches that an interposer may be an alternative layer upon which other semiconductor dies are placed (Nam: ¶¶25-26), and to provide for an additional processing capability as taught by Wilkerson (Wilkerson: ¶20).
Fuergut teaches that silicon oxide filler particles are known to produce thermally conductive molding compounds (¶66).
Furthermore, Wilkerson demonstrates forming four corner dies (each 200; Fig. 5) over the four corners of the first semiconductor die, such that each corner die is over at least one side of the first semiconductor die.
A PHOSITA would find it obvious to form the four corner dies (each of the four dies 221 of modified Nam in view of Yu) of modified Nam such that they are disposed over the four corners of the first semiconductor die as taught by Wilkerson, to provide for additional space between the corner dies of modified Nam, allowing for more of Nam’s thermally conductive (due to the silica, i.e., silicon oxide, fill material; Fuergut: ¶66) to be present in that space, allowing for better heat conduction (Wilkerson: “Accordingly, offsetting memory module 200 with respect to processor die 100 in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of processor die 100 having a higher power density.” (¶24)).
Doing so results in the first corner die being located over a side (Nam: bottom side as would be seen in Fig. 4A; see also Fig. 4B) of the first semiconductor die of modified Nam.
Wang teaches forming four corner dies (120a-120d; Fig. 15) with chamfered shapes (Fig. 15).
A PHOSITA would find it obvious to form the corner dies of modified Nam with chamfered shapes as taught by Wang to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first corner die of modified Nam having a first corner die first side (corresponding to the left side of Wang’s 120c), a first corner die second side (corresponding to the bottom side of Wang’s 120c), and a first corner die corner side (corresponding to the chamfered corner of Wang’s 120c) connecting the first corner die first side and the first corner die second side (See Wang’s Fig. 15).
(Re Claim 2) Modified Nam teaches the semiconductor module of claim 1, but has not been shown to explicitly teach the side of the first semiconductor die comprises a first semiconductor die first side, a first semiconductor die second side and a first semiconductor die first corner side connecting the first semiconductor die first side and the first semiconductor die second side, and at least one of:
the first corner die first side is outside the first semiconductor die first side;
the first corner die second side is outside the first semiconductor die second side; or the first corner die corner side is outside the first semiconductor die first corner side.
Wang teaches chamfering the corners of dies (Fig. 15).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to chamfer the four corners of the first semiconductor die to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first semiconductor die comprising a first semiconductor die first side (the left side of the first semiconductor die in plan view), a first semiconductor die second side (the bottom side of the first semiconductor die in plan view), and a first semiconductor die first corner side (the chamfered corner as taught by Wang that now connects the first semiconductor die first and first semiconductor die second side in a manner corresponding to that demonstrated by Wang’s 120c in Fig. 15), and at least one of:
the first corner die first side is outside the first semiconductor die first side (due to both a vertical and horizontal extension in view of Wilkerson).
the first corner die second side is outside the first semiconductor die second side; or the first corner die corner side is outside the first semiconductor die first corner side.
(Re Claim 4) Modified Nam teaches the semiconductor module of claim 1, but has not been explicitly shown to teach the first corner die corner side comprises a chamfered shape having a width less than or equal to 7 µm.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side as this is a width known to reduce cracking in encapsulating material.
Furthermore, prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Applicant’s width of 7 µm is unpatentably close to modified Nam’s width of about 7.070 µm. See In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°).
(Re Claim 5) Modified Nam teaches the semiconductor module of claim 2, wherein the first corner die corner side comprises a chamfered shape (Wang: Fig. 15) and the first semiconductor die first corner side comprises a chamfered shape (Wang: Fig. 15).
(Re Claim 8) Modified Nam taches the semiconductor module of claim 5, wherein the first corner die first side is substantially aligned with the first semiconductor die first side and the first corner die second side is substantially aligned with the first semiconductor die second side (in the manner shown by Wilkersons’ Fig. 5).
(Re Claim 9) Modified Nam teaches the semiconductor module of claim 5, wherein at least one of: the first corner die first side is located outside the first semiconductor die first side (due to horizontal spacing as shown by Wilkerson’s Fig. 5); or the first corner die second side is located outside the first semiconductor die second side.
Modified Nam has not been explicitly shown to teach the first corner die corner side is located outside the first semiconductor die first corner side.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side as this is a width known to reduce cracking in encapsulating material.
As both the first corner die and the first semiconductor die use the same offset distances as taught by Wang, the first corner die corner side will be located outside the first semiconductor die first corner side.
(Re Claim 10) Modified Nam teaches the semiconductor module of claim 5, wherein at least one of: the first corner die first side is located outside the first semiconductor die first side (due to horizontal spacing as shown by Wilkerson’s Fig. 5); or the first corner die second side is located outside the first semiconductor die second side.
Modified Nam has not been explicitly shown to teach the first corner die corner side is substantially aligned with the first semiconductor die first corner side.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side as this is a width known to reduce cracking in encapsulating material.
As both the first corner die and the first semiconductor die use the same offset distances as taught by Wang, the first corner die corner side will be located outside the first semiconductor die first corner side.
(Re Claim 11) Modified Nam teaches the semiconductor module of claim 2, wherein the first semiconductor die further comprises:
a first semiconductor die third side (the right side in plan view) and a first semiconductor die fourth side (the top side in plan view);
a first semiconductor die second corner side (analogous to Wang’s bottom right CS in Fig. 15) connecting the first semiconductor die second side and the first semiconductor die third side;
a first semiconductor die third corner side (analogous to Wang’s top left CS in Fig. 15) connecting the first semiconductor die first side and the first semiconductor die fourth side; and a first semiconductor die fourth corner side (analogous to Wang’s top right CS in Fig. 15) connecting the first semiconductor die third side and the first semiconductor die fourth side.
(Re Claim 12) Modified Nam teaches the semiconductor module of claim 11, further comprising:
a second corner die (Nam: bottom right 221; Fig. 4A) adjacent the second semiconductor die on the first semiconductor die and including a second corner die first side (right side; Fig. 4A), a second corner die second side (bottom side; Fig. 4A) and a second corner die corner side (analogous to Wang’s CS for 120d in Fig. 15) connecting the second corner die first side and the second corner die second side, wherein the second corner die is located over a side of the first semiconductor die (bottom side, in view of Wilkerson);
a third corner die (Nam: top left 221; Fig. 4A) adjacent the second semiconductor die on the first semiconductor die and including a third corner die first side (left side; Fig. 4A), a third corner die second side (top side; Fig. 4A) and a third corner die corner side (analogous to Wang’s CS for 120a in Fig. 15) connecting the third corner die first side and the third corner die second side, wherein the third corner die is located over a side of the first semiconductor die (top side, in view of Wilkerson); and
a fourth corner die (Nam: top right 221; Fig. 4A) adjacent the second semiconductor die on the first semiconductor die and including a fourth corner die first side (right side; Fig. 4A), a fourth corner die second side (top side; Fig. 4A) and a fourth corner die corner side (analogous to Wang’s CS for 120b in Fig. 15) connecting the fourth corner die first side and the fourth corner die second side, wherein the fourth corner die is located over a side of the first semiconductor die (top side, in view of Wilkerson).
(Re Claim 13) Modified Nam teaches the semiconductor module of claim 12, but has not been explicitly shown to teach the first corner die corner side is located outside the first semiconductor die first corner side, the second corner die corner side is located outside the first semiconductor die second corner side, the third corner die corner side is located outside the first semiconductor die third corner side, and the fourth corner die corner side is located outside the first semiconductor die fourth corner side.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first, second, third, and fourth corner die corner sides, as well as the first semiconductor die first, second, third, and fourth corner sides, as this is a width known to reduce cracking in encapsulating material.
As all corner sides use the same offset distances as taught by Wang, the first, second, third, and fourth corner die corner sides will be respectively located outside the first semiconductor die first, second, third, and fourth corner sides.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2022/0189907), Yu et al. (US 2014/0042643), Wilkerson et al. (US 2022/0392882) of record, Fuergut et al. (US 2022/0148934), and Wang et al. (US 2022/0310501) as applied to claim 5 above, and further in view of Jeon (US 2021/0407929).
(Re Claim 6) Modified Nam teaches the semiconductor module of claim 5, but has not been shown to explicitly teach the first corner die corner side is located outside the first semiconductor die first corner side and an overlap distance between the first corner die corner side and the first semiconductor die first corner side is greater than 1 µm.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side and the first semiconductor die first corner side, as this is a width known to reduce cracking in encapsulating material.
As both the first corner die and the first semiconductor die use the same offset distances as taught by Wang, the first die corner side will be located outside the first semiconductor die first corner side.
Jeon teaches using an overlap distance (L1 or L2; Fig. 1B_ of between 10 µm to 500 µm (¶37) between a first die (201; Fig. 1B) and another die (301 directly above 201; Fig. 1B).
A PHOSITA would find it obvious to form the first corner die such that the first corner die extends over the bottom and left side of the first semiconductor die, as would be seen in a plan view, by e.g., 255 µm, as taught Jeon, to ensure sufficient clearance between each corner die to allow for more thermally conductive material to be deposited between each corner die and on top of the first semiconductor die.
This results in an overlap distance between the first corner die corner side and the first semiconductor die first corner side being greater than 1 µm (the distance is at least e.g., 255 µm).
Claims 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2022/0189907), Yu et al. (US 2014/0042643), Wilkerson et al. (US 2022/0392882) of record, Fuergut et al. (US 2022/0148934), Wang et al. (US 2022/0310501), and Yeh et al. (US 2017/0125376).
(Re Claim 14) Nam teaches method of forming a semiconductor module, the method comprising:
forming a second semiconductor die (222; Fig. 4A); and
forming a first corner die (bottom left 221; Fig. 4A) adjacent to the second semiconductor die on the first semiconductor die.
Nam has not been explicitly shown to teach attaching a first semiconductor die to a first carrier substrate;
forming a backside metal bonding pad on a backside of the first semiconductor die;
forming a die bonding film on the backside of the first semiconductor die such that the backside metal bonding pad is exposed through the die bonding film;
attaching a second semiconductor die to the first semiconductor die by a hybrid bond, wherein a frontside metal bonding pad of the second semiconductor die is bonded to the backside metal bonding pad of the first semiconductor die and a second semiconductor die bonding film of the second semiconductor die is bonded to the die bonding film; and
attaching a first corner die to the first semiconductor die adjacent the second semiconductor die such that the first corner die is over a side of the first semiconductor die, wherein the first corner die includes a first corner die first side, a first corner die second side and a first corner die corner side connecting the first corner die first side and the first corner die second side.
Yu teaches forming a second semiconductor die (301; Fig. 3B) surrounded by four corner dies (303; Fig. 3B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form four corner dies (each 221; Fig. 4A) of Nam surrounding the second semiconductor die, as arranged in Yu, instead of the six corner dies, to reduce the number of die attachment steps when forming the semiconductor module.
Nam teaches that a base (101; Fig. 1D) having a plurality of semiconductor dies placed on it (¶25) may be either an interposer or a semiconductor die (¶26).
Wilkerson teaches forming a first semiconductor die (100; Fig. 5 and 7); and attaching a first corner die (200; Fig. 5) to the first semiconductor die, wherein the first corner die is located over a side (left side; Fig. 5) of the first semiconductor die.
A PHOSITA would find it obvious to form the interposer 101a of Nam as the first semiconductor die, as Nam teaches that an interposer may be an alternative layer upon which other semiconductor dies are placed (Nam: ¶¶25-26), and to provide for an additional processing capability as taught by Wilkerson (Wilkerson: ¶20).
Fuergut teaches that silicon oxide filler particles are known to produce thermally conductive molding compounds (¶66).
Furthermore, Wilkerson demonstrates forming four corner dies (each 200; Fig. 5) over the four corners of the first semiconductor die, such that each corner die is over at least one side of the first semiconductor die.
A PHOSITA would find it obvious to form the four corner dies (each of the four dies 221 of modified Nam in view of Yu) of modified Nam such that they are disposed over the four corners of the first semiconductor die as taught by Wilkerson, to provide for additional space between the corner dies of modified Nam, allowing for more of Nam’s thermally conductive (due to the silica, i.e., silicon oxide, fill material; Fuergut: ¶66) to be present in that space, allowing for better heat conduction (Wilkerson: “Accordingly, offsetting memory module 200 with respect to processor die 100 in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of processor die 100 having a higher power density.” (¶24)).
Doing so results in the first corner die being located over a side (Nam: bottom side as would be seen in Fig. 4A; see also Fig. 4B) of the first semiconductor die of modified Nam.
Wang teaches forming four corner dies (120a-120d; Fig. 15) with chamfered shapes (Fig. 15).
A PHOSITA would find it obvious to form the corner dies of modified Nam with chamfered shapes as taught by Wang to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first corner die of modified Nam having a first corner die first side (corresponding to the left side of Wang’s 120c), a first corner die second side (corresponding to the bottom side of Wang’s 120c), and a first corner die corner side (corresponding to the chamfered corner of Wang’s 120c) connecting the first corner die first side and the first corner die second side (See Wang’s Fig. 15).
Yeh teaches attaching a first semiconductor die (102A; Fig. 22) to a first carrier substrate (112; Fig. 22);
forming a backside metal bonding pad (602; Fig. 22) on a backside (top side in Fig. 22) of the first semiconductor die;
forming a die bonding film (118) on the backside of the first semiconductor die such that the backside metal bonding pad is exposed through the die bonding film (Fig. 22);
attaching a second semiconductor die (102B; Fig. 22) to the first semiconductor die by a hybrid bond (¶53), wherein a frontside metal bonding pad (110B; Fig. 22) of the second semiconductor die is bonded to the backside metal bonding pad of the first semiconductor die and a second semiconductor die bonding film (108B; Fig. 22) of the second semiconductor die is bonded to the die bonding film.
A PHOSITA would find it obvious to form a backside metal bonding pad (Yeh: 602; Fig. 22) on a backside (Yeh: top side in Fig. 22) of the first semiconductor die;
form a die bonding film (Yeh: 118) on the backside of the first semiconductor die such that the backside metal bonding pad is exposed through the die bonding film (Yeh: Fig. 22);
and attach the second semiconductor die (Nam: 222; Fig. 4A) to the first semiconductor die by a hybrid bond (Yeh: ¶53), wherein a frontside metal bonding pad (Nam: 222p; Fig. 4B) of the second semiconductor die is bonded to the backside metal bonding pad of the first semiconductor die, as hybrid bonding allows for less space dedicated to the connections compared to using solder bonding.
Furthermore, a PHOSITA would find it obvious to form the second semiconductor die of modified Nam with a bonding film as taught by Yeh, to secure the frontside metal bonding pad of the second semiconductor die and protect the active devices of the second semiconductor.
This results in modified Nam teaching the second semiconductor die bonding film (corresponding to Yeh’s 108B) of the second semiconductor die is bonded to the die bonding film.
(Re Claim 15) Modified Nam teaches the method of claim 14, but has not been explicitly shown teach the side of the first semiconductor die comprises a first semiconductor die first side, a first semiconductor die second side and a first semiconductor die first corner side connecting the first semiconductor die first side and the first semiconductor die second side, and the attaching of the first corner die to the first semiconductor die comprises attaching the first corner die to the first semiconductor die such that at least one of:
the first corner die first side is outside the first semiconductor die first side;
the first corner die second side is outside the first semiconductor die second side; or the first corner die corner side is outside the first semiconductor die first corner side.
Wang teaches chamfering the corners of dies (Fig. 15).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to chamfer the four corners of the first semiconductor die to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first semiconductor die comprising a first semiconductor die first side (the left side of the first semiconductor die in plan view), a first semiconductor die second side (the bottom side of the first semiconductor die in plan view), and a first semiconductor die first corner side (the chamfered corner as taught by Wang that now connects the first semiconductor die first and first semiconductor die second side in a manner corresponding to that demonstrated by Wang’s 120c in Fig. 15), and attaching he first corner die to the first semiconductor die comprises attaching the first corner die to the first semiconductor die such that at least one of least one of:
the first corner die first side is outside the first semiconductor die first side (due to both a vertical and horizontal extension in view of Wilkerson).
the first corner die second side is outside the first semiconductor die second side; or the first corner die corner side is outside the first semiconductor die first corner side.
(Re Claim 17) Modified Nam teaches the method of claim 14, further comprising:
forming the first corner die such that a surface of the first corner die corner side comprises one of a flat surface (from chamfering in view of Wang) or a wavy surface.
(Re Claim 18) Modified Nam teaches the method of claim 14, but has not been explicitly shown to teach the method further comprising:
forming the first corner die such that the first corner die corner side comprises a chamfered shape having a length less than or equal to 7 µm.
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side as this is a width known to reduce cracking in encapsulating material.
Furthermore, prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Applicant’s width of 7 µm is unpatentably close to modified Nam’s width of about 7.070 µm. See In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2022/0189907), Yu et al. (US 2014/0042643), Wilkerson et al. (US 2022/0392882) of record, Fuergut et al. (US 2022/0148934), Wang et al. (US 2022/0310501), and Yeh et al. (US 2017/0125376) as applied to claim 18 above, and further in view of Jeon (US 2021/0407929).
(Re Claim 19) Modified Nam teaches the method of claim 18, but has not been explicitly shown to teach the side of the first semiconductor die comprises a first semiconductor die first side, a first semiconductor die second side and a first semiconductor die first corner side connecting the first semiconductor die first side and the first semiconductor die second side, wherein the first corner die corner side comprises a chamfered shape and the first semiconductor die first corner side comprises a chamfered shape, and wherein the attaching of the first corner die to the first semiconductor die comprises attaching the first corner die to the first semiconductor die such that one of:
the first corner die corner side is located outside the first semiconductor die first corner side and an overlap distance between the first corner die corner side and the first semiconductor die first corner side is greater than 1 µm; or the first corner die corner side is located inside the first semiconductor die first corner side and a distance between the first corner die corner side and the first semiconductor die first corner side is less than 1000 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to chamfer the four corners of the first semiconductor die to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first semiconductor die comprising a first semiconductor die first side (the left side of the first semiconductor die in plan view), a first semiconductor die second side (the bottom side of the first semiconductor die in plan view), and a first semiconductor die first corner side (the chamfered corner as taught by Wang that now connects the first semiconductor die first and first semiconductor die second side in a manner corresponding to that demonstrated by Wang’s 120c in Fig. 15), wherein the first corner die corner side comprises a chamfered shape and the first semiconductor die first corner side comprises a chamfered shape (Wang: Fig. 15).
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side and the first semiconductor die first corner side, as this is a width known to reduce cracking in encapsulating material.
As both the first corner die and the first semiconductor die use the same offset distances as taught by Wang, the first die corner side will be located outside the first semiconductor die first corner side.
Jeon teaches using an overlap distance (L1 or L2; Fig. 1B_ of between 10 µm to 500 µm (¶37) between a first die (201; Fig. 1B) and another die (301 directly above 201; Fig. 1B).
A PHOSITA would find it obvious to form the first corner die such that the first corner die extends over the bottom and left side of the first semiconductor die, as would be seen in a plan view, by e.g., 255 µm, as taught Jeon, to ensure sufficient clearance between each corner die to allow for more thermally conductive material to be deposited between each corner die and on top of the first semiconductor die.
This results in the first corner die corner side is located outside the first semiconductor die first corner side (due to the vertical and horizontal spacing in view of Wilkerson and Jeon) and an overlap distance between the first corner die corner side and the first semiconductor die first corner side being greater than 1 µm (the distance is at least e.g., 255 µm).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2022/0189907), Yu et al. (US 2014/0042643), Wilkerson et al. (US 2022/0392882) of record, Fuergut et al. (US 2022/0148934), Wang et al. (US 2022/0310501), and Jeon (US 2021/0407929).
(Re Claim 20) Nam teaches a package structure, comprising:
a package substrate (310; Fig. 6);
a semiconductor module (the components corresponding to 10c as shown in Fig. 4A-4B) on the package substrate, comprising:
a second semiconductor die (222; Fig. 4A) on the first semiconductor die; and
a first corner die (lower left 221; Fig. 4A) adjacent the second semiconductor die;
a thermal interface material (TIM) layer (350; Fig. 6, ¶98) on the semiconductor module; and
a package lid (340; Fig. 6) on the semiconductor module and attached to the package substrate, wherein the package lid includes a package lid plate portion (portion of the package lid above 350; Fig. 6) on the TIM layer and a package lid foot portion (remaining part of the package lid; Fig. 6) projecting from the package lid plate portion and attached to the package substrate.
Nam has not been shown to explicitly teach a package structure comprising:
a first semiconductor die including a first semiconductor die first corner side comprising a chamfered shape;
a second semiconductor die on the first semiconductor die; and
a first corner die adjacent the second semiconductor die on the first semiconductor die and including a first corner die corner side comprising a chamfered shape and located outside the first semiconductor die first corner side by an overlap distance greater than 1 µm.
Yu teaches forming a second semiconductor die (301; Fig. 3B) surrounded by four corner dies (303; Fig. 3B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize four corner dies (each 221; Fig. 4A) of Nam surrounding the second semiconductor die, as arranged in Yu, instead of the six corner dies, to reduce the number of die attachment steps when forming the semiconductor module.
Nam teaches that a base (101; Fig. 1D) having a plurality of semiconductor dies placed on it (¶25) may be either an interposer or a semiconductor die (¶26).
Wilkerson teaches forming a first semiconductor die (100; Fig. 5 and 7); and a first corner die (200; Fig. 5), wherein the first corner die is located over a side (left side; Fig. 5) of the first semiconductor die.
A PHOSITA would find it obvious to form the interposer 101a of Nam as the first semiconductor die, as Nam teaches that an interposer may be an alternative layer upon which other semiconductor dies are placed (Nam: ¶¶25-26), and to provide for an additional processing capability as taught by Wilkerson (Wilkerson: ¶20).
Fuergut teaches that silicon oxide filler particles are known to produce thermally conductive molding compounds (¶66).
Furthermore, Wilkerson demonstrates forming four corner dies (each 200; Fig. 5) over the four corners of the first semiconductor die, such that each corner die is over at least one side of the first semiconductor die.
A PHOSITA would find it obvious to form the four corner dies (each of the four dies 221 of modified Nam in view of Yu) of modified Nam such that they are disposed over the four corners of the first semiconductor die as taught by Wilkerson, to provide for additional space between the corner dies of modified Nam, allowing for more of Nam’s thermally conductive (due to the silica, i.e., silicon oxide, fill material; Fuergut: ¶66) to be present in that space, allowing for better heat conduction (Wilkerson: “Accordingly, offsetting memory module 200 with respect to processor die 100 in a three-dimensional integrated circuit structure provides space to position a lower thermal resistance path structure directly on top of a region of processor die 100 having a higher power density.” (¶24)).
Doing so results in the first corner die being located over a side (Nam: bottom side as would be seen in Fig. 4A; see also Fig. 4B) of the first semiconductor die of modified Nam.
Wang teaches forming four corner dies (120a-120d; Fig. 15) with chamfered shapes (Fig. 15).
A PHOSITA would find it obvious to form the corner dies of modified Nam with chamfered shapes as taught by Wang to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first corner die of modified Nam having a first corner die first side (corresponding to the left side of Wang’s 120c), a first corner die second side (corresponding to the bottom side of Wang’s 120c), and a first corner die corner side (corresponding to the chamfered corner of Wang’s 120c) connecting the first corner die first side and the first corner die second side (See Wang’s Fig. 15) comprising a chamfered shape.
Wang teaches chamfering the corners of dies (Fig. 15).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to chamfer the four corners of the first semiconductor die to reduce cracking causes by sharp corners of the corner dies (Wang: ¶37).
This results in the first semiconductor die comprising a first semiconductor die first side (the left side of the first semiconductor die in plan view), a first semiconductor die second side (the bottom side of the first semiconductor die in plan view), and a first semiconductor die first corner side (the chamfered corner as taught by Wang that now connects the first semiconductor die first and first semiconductor die second side in a manner corresponding to that demonstrated by Wang’s 120c in Fig. 15) having a chamfered shape,
Wang teaches that an offset distance D1 and D2 may be equal to about 5 µm (Fig. 3, ¶37).
Using the provided value of about 5 µm for both D1 and D2, the chamfered shape of Wang’ Fig. 3 has a width of about 7.070 µm.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize that particular width for the first corner die corner side and the first semiconductor die first corner side, as this is a width known to reduce cracking in encapsulating material.
As both the first corner die and the first semiconductor die use the same offset distances as taught by Wang, the first die corner side will be located outside the first semiconductor die first corner side.
Jeon teaches using an overlap distance (L1 or L2; Fig. 1B_ of between 10 µm to 500 µm (¶37) between a first die (201; Fig. 1B) and another die (301 directly above 201; Fig. 1B).
A PHOSITA would find it obvious to form the first corner die such that the first corner die extends over the bottom and left side of the first semiconductor die, as would be seen in a plan view, by e.g., 255 µm, as taught Jeon, to ensure sufficient clearance between each corner die to allow for more thermally conductive material to be deposited between each corner die and on top of the first semiconductor die.
This results the first corner die corner side located outside the first semiconductor die first corner side by an overlap distance greater than 1 µm (the distance is at least e.g., 255 µm).
Conclusion
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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