DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/13/2024. Claims 1-10 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 05/13/2024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS).
PNG
media_image1.png
543
713
media_image1.png
Greyscale
Regarding claim 1. Yang discloses a semiconductor device, comprising:
a substrate (Fig 1, substrate 102, Para [ 0008]);
a gate structure (gate structure [ 112,110], construed as gate structure, Para [ 0008]) positioned on the substrate (Fig 1, substrate 102, Para [ 0008]);
an inner spacer layer (Fig 1, “inner spacer 118 can cover the gate electrode 110 completely”, Para [ 0012]) positioned on the substrate (Fig 1, substrate 102, Para [ 0008]) and covering the gate structure (inner spacer 118, Para [ 0012]); and
a plurality of spacer layers (Fig 1, spacers [116], Para [ 0012-0013]) positioned on sides of the inner spacer layer (inner spacer 118, Para [ 0012]) with the gate structure (gate structure [ 112,110], Para [ 0008]) in between and positioned on the substrate (Fig 1, substrate 102, Para [ 0008]).
But Yang does not disclose explicitly antiferroelectric spacer layers.
In a similar field of endeavor, KAVALIEROS discloses antiferroelectric spacer layers (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “antiferroelectric spacer layers (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 2. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 5. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose wherein the plurality of antiferroelectric spacer layers comprise dopants (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the plurality of antiferroelectric spacer layers comprise dopants (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 6. Yang and KAVALIEROS disclose the semiconductor device of claim 5, KAVALIEROS further disclose wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium (Para [ 0042-0043]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the dopants comprise silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium (Para [ 0042-0043])” for further advantage such as providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material.
.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) as applied claims above and further in view of SHARANGPANI et al (US 2021/0050371 A1; hereafter SHARANGPANI).
Regarding claim 3. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043], which is same material discloses instant application).
But Yang and KAVALIEROS does not disclose explicitly spacer layers are crystalline.
In a similar field of endeavor, KAVALIEROS discloses spacer layers are crystalline (Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “wherein the plurality of antiferroelectric spacer layers are crystalline (Para [ 0093])” for further advantage such as enables stable integration process with a spacer structure which comprises an (anti)ferromagnetic material.
Regarding claim 4. Yang and KAVALIEROS disclose the semiconductor device of claim 1, KAVALIEROS further disclose plurality of antiferroelectric spacer layers comprise hafnium and oxygen or zirconium and oxygen (Para [ 0042-0043], which is same material discloses instant application)
But Yang and KAVALIEROS does not disclose explicitly spacer layers are tetragonal.
In a similar field of endeavor, KAVALIEROS discloses spacer layers are crystalline (Para [ 0093]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang in light of KAVALIEROS teaching “spacer layers are crystalline (Para [ 0093])” for further advantage such as enables stable integration process with a spacer structure which comprises an (anti)ferromagnetic material.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) as applied claims above and further in view of Qin et al (US 2014/0217519 A1; hereafter Qin).
Regarding claim 7. Yang and KAVALIEROS disclose the semiconductor device of claim 1, But Yang and KAVALIEROS does not disclose explicitly further comprising a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure, defining a channel region between the plurality of recesses and under the gate structure.
In a similar field of endeavor, Qin discloses a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure (Fig 2-4, Para [ 0030-0034]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0030-0034]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of Qin teaching “a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure (Fig 2-4, Para [ 0030-0034]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0030-0034])” for further advantage such as effectively improve the performances of the transistor.
Regarding claim 8. Yang and KAVALIEROS in light of Qin discloses the semiconductor device of claim 7, Qin further discloses further comprising a plurality of impurity regions comprising:
a plurality of lightly doped portions (Fig 7, LDD regions 18, Para [ 0027]) positioned within the substrate (substrate 10, Para [ 0030]) and separated from each other with the channel region in between (Para [ 0034]); and a plurality of bulk doped portions (Halo material layer 15, Para [ 0034]) positioned within the substrate (substrate 10, Para [ 0030]), respectively connected to the plurality of lightly doped portions (LDD regions 18, Para [ 0027]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of Qin teaching “a plurality of impurity regions comprising: a plurality of lightly doped portions ( Fig 7, LDD regions 18, Para [ 0027]) positioned within the substrate ( substrate 10, Para [ 0030]) and separated from each other with the channel region in between (Para [ 0034]); and a plurality of bulk doped portions (Halo material layer 15, Para [ 0034]) positioned within the substrate ( substrate 10, Para [ 0030]), respectively connected to the plurality of lightly doped portions ( LDD regions 18, Para [ 0027])” for further advantage such as effectively improve the performances of the transistor.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2014/0117467 A1; hereafter Yang) in view of KAVALIEROS et al (US 2020/0312978 A1; hereafter KAVALIEROS) as applied claims above and further in view of LU et al (US 2023/0402457 A1; hereafter LU).
Regarding claim 9. Yang and KAVALIEROS disclose the semiconductor device of claim 8, But Yang and KAVALIEROS does not disclose explicitly wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60.
In a similar field of endeavor, LU discloses wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60 (Fig 2, Para [ 0099] discloses “upper conductive portion 212U of the gate region 212 has a vertical thickness TV about 10 nm to 15 nm” and Para [ 0111] discloses “the lower conductive portion 212L of the gate region 212 is around 2 nm to 4 nm or less” and “a vertical thickness of the N type LDD region is less than 20 nm, Para [ 0017]. Based on the combine gate region thickness and LDD thickness less 20 nm, maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions desired ratio can be achieved. Examiner interpreted LDD region is less than 20 nm, can be any range less than 20 nm, which can be applied for the claim limitation).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of LU teaching “a plurality of recesses recessed from a top surface of the substrate, adjacent to the gate structure (Fig 2-4, Para [ 0030-0034]), defining a channel region between the plurality of recesses and under the gate structure (Fig 2-4, Para [ 0030-0034])” for further advantage such as minimizes current leakages, increases channel-conduction performance and control, and optimizes functions of source and drain regions.
Examiner like to note that, applicant has not presented persuasive evidence that the claimed “wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed ratio). Also, the applicant has not shown that the claimed ratio 7.00 and about 3.60 produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It has been held that it is a prima facie obvious by change of size in view of In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), see MPEP 2144.04.
Regarding claim 10. Yang and KAVALIEROS disclose the semiconductor device of claim 8, But Yang and KAVALIEROS does not disclose explicitly wherein a ratio of a thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20.
In a similar field of endeavor, LU discloses wherein a ratio of a thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20 (Fig 2, Para [ 0099] discloses “upper conductive portion 212U of the gate region 212 has a vertical thickness TV about 10 nm to 15 nm” and Para [ 0111] discloses “the lower conductive portion 212L of the gate region 212 is around 2 nm to 4 nm or less” and “a vertical thickness of the N type LDD region is less than 20 nm, Para [ 0017]. Based on the combine gate region thickness and LDD thickness less 20 nm, “a ratio of a thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20” can be achieved. Examiner interpreted LDD region is less than 20 nm, any range less than 20 nm, can be applied for the claim limitation).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yang and KAVALIEROS in light of LU teaching “wherein a ratio of a thickness of the gate structure to a maximal depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.60 (Fig 2, Para [ 0099] discloses “upper conductive portion 212U of the gate region 212 has a vertical thickness TV about 10 nm to 15 nm” and Para [ 0111] discloses “the lower conductive portion 212L of the gate region 212 is around 2 nm to 4 nm or less” and “a vertical thickness of the N type LDD region is less than 20 nm, Para [ 0017]. Based on the combine gate region thickness and LDD thickness less 20 nm, a ratio of a thickness of the gate structure to a thickness of the plurality of lightly doped portions can be achieved. Examiner interpreted LDD region is less than 20 nm, can be any range less than 20 nm, which can be applied for the claim limitation)” for further advantage such as minimizes current leakages, increases channel-conduction performance and control, and optimizes functions of source and drain regions.
Examiner like to note that, applicant has not presented persuasive evidence that the claimed “forming a gate isolation layer on the main surface of the device cell over the structure having a second length at least twice as long as the first length” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed reduced width). Also, the applicant has not shown that the claimed a second length at least twice as long as the first length produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
It has been held that it is a prima facie obvious by change of size in view of In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), see MPEP 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights