CTNF 18/662,021 CTNF 90001 DETAILED ACTION Examiner’s Note The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims. Applicant is requested to review those prior arts to overcome the future rejection using these arts. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Notes Claim 1, lines 17-20 repeats below limitations: wherein an angle defined between the second side of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90° For examination, these limitations will be deleted as below: 1. A semiconductor package, comprising: a semiconductor die, having I/O pads arranged at an active side of the semiconductor die; a package substrate, with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening penetrating through the package substrate, wherein the I/O pads are overlapped with the opening, and a width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate; and bonding wires, connecting the I/O pads to the second side of the package substrate through the opening of the package substrate; wherein a sidewall of the opening across which a group of the bonding wires extend is a curved sidewall; wherein an angle defined between the second side of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90° wherein an angle defined between the second side of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90°. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-3 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US 5777391 A, hereinafter Nakamura’391) . Regarding independent claim 1 , Nakamura’391 teaches, “A semiconductor package (fig. 1-16, related descriptions), comprising: a semiconductor die (2, fig. 12, also see fig. 2-3, column 7, lines 21-33), having I/O pads (2A) arranged at an active side (side of main surface) of the semiconductor die; a package substrate (1, base substrate), with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening (5) penetrating through the package substrate (1), wherein the I/O pads (2A) are overlapped with the opening (5), and a width of the opening (5) at the second side of the package substrate (1) is greater than a width of the opening (5) at the first side of the package substrate (1); and bonding wires (6), connecting the I/O pads (2A) to the second side of the package substrate (1) through the opening (5) of the package substrate (1); wherein a sidewall of the opening (5) across which a group of the bonding wires (6) extend is a curved sidewall; wherein an angle defined between the second side of the package substrate (1) and a sidewall of the opening (5) across which a group of the bonding wires extend is greater than 90° wherein an angle defined between the second side of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90°. Regarding claim 2 , Nakamura’391 further teaches, “The semiconductor package according to claim 1, wherein an angle defined between the first side of the package substrate (1) and the sidewall of the opening (5) is less than 90° (fig. 12). Regarding claim 3 , Nakamura’391 further teaches, “The semiconductor package according to claim 2, wherein the sidewall of the opening (5) is a sloped sidewall (fig. 12)”. PNG media_image1.png 471 918 media_image1.png Greyscale Regarding independent claim 12 , Nakamura’391 teaches, “A semiconductor package (fig. 1-16, related descriptions), comprising: a semiconductor die (2, fig. 12, also see fig. 2-3, column 7, lines 21-33), having I/O pads (2A) arranged at an active side (side of main surface) of the semiconductor die; a package substrate (1, base substrate), with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and having an opening (5) penetrating through the package substrate (1), wherein the I/O pads (2A) are overlapped with the opening (5), and a width of the opening (5) at the second side of the package substrate (1) is greater than a width of the opening (5) at the first side of the package substrate (1); bonding wires (6), connecting the I/O pads (2A) to the second side of the package substrate (1) through the opening (5) of the package substrate (1); a first encapsulant (7/7A), laterally encapsulating the semiconductor die (2); Aa second encapsulant (7/), filling up the opening (5) and extending to the second side of the package substrate (1); and conductive pads (1A, 1B), disposed at the second side of the package substrate (1), and connected to the bonding wires (6); wherein a portion of the second encapsulant (7/7A) filled in the opening (5) has a first width at the first side of the package substrate (1) and a second width at the second side of the package substrate (1), and the second width is greater than the first width”. Regarding claim 13 , Nakamura’391 further teaches, “The semiconductor package according to claim 12, wherein the conductive pads (1A, 1B) are covered by the second encapsulant (7/7A)”. Regarding claim 14 , Nakamura’391 further teaches, “The semiconductor package according to claim 12, wherein the opening (5, fig. 13) has long sides and short sides, and the conductive pads (1A) are arranged along the long sides of the opening” . 07-21-aia AIA Claim s 1 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Camacho et al. (US 20090243064 A1, hereinafter Camacho’064) . Regarding independent claim 1 , Camacho’064 teaches, “A semiconductor package (fig. 1-18, ¶ [0030] - ¶ [0057]), comprising: a semiconductor die (308, fig. 14), having I/O pads (310) arranged at an active side of the semiconductor die; a package substrate (280), with a first side (top side) attached to the active side of the semiconductor die (308) and a second side (bottom) facing away from the semiconductor die (308), and having an opening (282) penetrating through the package substrate (280), wherein the I/O pads (310) are overlapped with the opening (280), and a width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate; and bonding wires (315-316), connecting the I/O pads (310) to the second side of the package substrate (280) through the opening (282) of the package substrate (280); wherein a sidewall of the opening (282) across which a group of the bonding wires (314, 315) extend is a curved sidewall; wherein an angle defined between the second side (bottom side) of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90° wherein an angle defined between the second side of the package substrate and a sidewall of the opening across which a group of the bonding wires extend is greater than 90°. Regarding claim 4 , Camacho’064 further teaches, “The semiconductor package according to claim 1, wherein the sidewall of the opening (282, fig. 14) extends from the second side of the package substrate (280) to a joint shared with another sidewall of the opening extending from the joint to the first side of the package substrate (280)”. Regarding claim 5 , Camacho’064 further teaches, “The semiconductor package according to claim 4, wherein an angle defined between the first side of the package substrate (280) and the sidewall of the opening (282) extending from the joint to the first side of the package substrate is equal to or less than 90°” . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-22-aia AIA Claim s 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Camacho’064 as applied to claim 5 above, and further in view of SIRINORAKUL; Saravuth et al. (US 20220028798 A1, hereinafter Siri’798) . Regarding claim 6 , Camacho’064 teaches all the limitations described in claim 5. But Camacho’064 is silent upon the provision of wherein the sidewall arches into the package substrate. However, Siri’798 teaches a similar semiconductor package with leadframe, wherein the sidewall (216, fig. 2C) arches into the package substrate (210)”. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Camacho’064 and Siri’798 to include leadframe with arched sidewalls according to the teachings of Siri’798 with a general motivation of providing enhanced adhesion for the package device. Regarding claim 7 , Camacho’064 modified with Siri’798 further teaches, “The semiconductor package according to claim 5, wherein the sidewall is rounded into opening (fig. 2C, Siri’798) . 07-21-aia AIA Claim s 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over YOO et al. (US 20120187437 A1, hereinafter Yoo’437) in view of Camacho’064 and Siri’798 . Regarding independent claim 8 , Yoo’437 teaches, “A semiconductor package (fig. 1-11; ¶ [0041] - ¶ [0063]), comprising: a semiconductor die (104, fig. 1), having I/O pads (connected to bonding wires 106) arranged at an active side (bottom side) of the semiconductor die (104); a package substrate (101), with a first side (top side) attached to the active side of the semiconductor die (104) and a second side (bottom side) facing away from the semiconductor die (104), and laterally surrounding an opening (102), wherein the I/O pads are overlapped with the opening (102), the opening has long sides and short sides, ((a width across the long sides of the opening at the second side of the package substrate is greater than a width across the long sides the opening at the first side of the package substrate; and)) bonding wires (106), connecting the I/O pads to the second side of the package substrate (101) across the long sides of the opening (102, fig. 3A-3B); wherein a length across the short sides (e.g., the sort side of the opening 102, figs. 3A-3B) of the opening (e.g., the opening in fig. 4C) at the second side (e.g., the bottom side of the substrate 101 in fig. 4C) of the package substrate (101, fig. 4C) is substantially equal to a length across the short sides (e.g., the sort side of the opening 102, figs. 3A-3B) of the opening (e.g., the opening in fig. 4C) at the first side of the package substrate (101, fig. 4C); ((wherein each long side of the opening is defined by a curved sidewall.)) But Yoo’437 is silent upon the provision of wherein a width across the long sides of the opening at the second side of the package substrate is greater than a width across the long sides the opening at the first side of the package substrate; and However, Camacho’064 teaches a similar package (fig. 12), wherein a width across the long sides of the opening (282) at the second side (bottom side) of the package substrate (280) is greater than a width across the long sides of the opening (282) at the first side (top side) of the package substrate (280); Yoo’437 and Camacho’064 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoo’437 with the features of Camacho’064 because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yoo’437 and Camacho’064 to include a wider opening according to the teachings of Camacho’064 with a motivation of providing more room for wiring and enhanced adhesion for the package device. Yoo’437 modified with Camacho’064 is silent upon the provision of wherein each long side of the opening is defined by a curved sidewall. However, Siri’798 teaches a similar semiconductor package, wherein each long side of the opening (fig. 2C) is defined by a curved sidewall (of the package substrate 210/216). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yoo’437 modified with Camacho’064 and Siri’798 to include package substrate with curved sidewalls according to the teachings of Siri’798 with a general motivation of providing enhanced adhesion for the package device. Regarding claim 9 , Yoo’437 modified with Camacho’064 and Siri’798 further teaches, “The semiconductor package according to claim 8, wherein a length across the short sides of the opening (102, figs. 3A-3B, Yoo’437) at the second side (fig. 8) of the package substrate (101) is greater than a length across the short sides of the opening (102, figs. 3A-3B, Yoo’437) at the first side of the package substrate”. Regarding claim 10 , Yoo’437 modified with Camacho’064 and Siri’798 further teaches, “The semiconductor package according to claim 8, wherein each long side of the opening is defined by a sloped sidewall (fig. 12, Camacho’064)”. Regarding claim 11 , Yoo’437 modified with Camacho’064 and Siri’798 further teaches, “The semiconductor package according to claim 8, wherein each long side of the opening is defined by a first sidewall and a second sidewall jointed with the first sidewall, and extending directions of the first and second sidewalls are different from each other (fig. 12, Camacho’064)”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817 Application/Control Number: 18/662,021 Page 2 Art Unit: 2817 Application/Control Number: 18/662,021 Page 3 Art Unit: 2817 Application/Control Number: 18/662,021 Page 4 Art Unit: 2817 Application/Control Number: 18/662,021 Page 5 Art Unit: 2817 Application/Control Number: 18/662,021 Page 6 Art Unit: 2817 Application/Control Number: 18/662,021 Page 7 Art Unit: 2817 Application/Control Number: 18/662,021 Page 8 Art Unit: 2817 Application/Control Number: 18/662,021 Page 9 Art Unit: 2817 Application/Control Number: 18/662,021 Page 10 Art Unit: 2817 Application/Control Number: 18/662,021 Page 11 Art Unit: 2817 Application/Control Number: 18/662,021 Page 12 Art Unit: 2817
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