Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (17/460,178) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/13/2024 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 4-5 and 8-20 is/are objected to because of the following informalities where proposed corrections have been bolded and underlined:
Claim 4, lines 4-5, “portions of the additional photoresist layer [[does]] do not cover” in order to be grammatically correct;
Claim 8, lines 25-27, “the first contact assembly is formed entirely within an area of [[said]] a surface segment of the topmost surface of the layer stack” as this is the first recitation of a surface segment of the topmost surface of the layer stack in this line of claims;
Claim 15, lines 2-4, “a horizontal top surface that extends over . . . [[the]] a second horizontally-extending portion of the dielectric fill material layer” since this is the first recitation of a second horizontally-extending portion of the dielectric fill because claim 15 does not depend on claim 14;
Claim 16, lines 31-33, “the first contact assembly is formed entirely within an area of [[said]] a surface segment of the topmost surface of the layer stack” for the same reason as claim 8 above.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-7 and 18-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the final three lines of the claim recite “a first tubular insulating spacer that is formed directly on a first cylindrical sidewall of the second metallic electrode layer and directly on a first cylindrical sidewall of the third metallic electrode layer”. This is the first recitation of a second and third metallic electrode layer in claim 1. However, earlier in the claim, there was a recitation of “a layer stack including at least three metallic electrode layers”. It is therefore unclear if the second and third metallic electrode layers are part of the at least three metallic electrode layers or if they represent metallic electrode layers which are separate from the at least three previously required. For this reason, claim 1 is rejected under 35 U.S.C. 112(b) and claims 2-7 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, claim 1 will be interpreted to read as “a first tubular insulating spacer that is formed directly on a first cylindrical sidewall of [[the]] a second metallic electrode layer of the at least three metallic electrode layers and directly on a first cylindrical sidewall of [[the]] a third metallic electrode layer of the at least three metallic electrode layers”
Regarding Claim 5, the claim recites “vertically extending the first via cavity through another (singular) metallic electrode layers (plural) selected from the at least three metallic electrode layers” in the second line of the claim. Claim 5 depends on claim 3 which has previously recited “vertically extending the first subset of the via cavities through two metallic electrode layers selected from the at least three metallic electrode layers”. Claim 3 therefore requires etching through two layers of the at least three layers and claim 5 is unclear as to how many layers must further be etched through or if this is referring to multiple of the previous two metallic electrode layers. The use of the word layers (plural) in claim 5 would suggest at least two such that the at least three metallic electrode layers may now comprise at least four layers (i.e. two for claim 3 and another two for claim 5). However, the use of the word another in claim 5 is more grammatically correct in referring to a single layer (i.e. ‘another metallic electrode layer’ as opposed to ‘other metallic electrode layers’) such that the stack may still comprise only three metallic electrode layers. It is therefore unclear what the relationship is of the another metallic electrode layers is to the first two metallic electrode layers and how many total metallic electrode layers are required. For this reason, claim 5 is rejected under 35 U.S.C. 112(b). For the purposes of this examination, claim 5 will be interpreted to read as “vertically extending the first via cavity through another metallic electrode layer selected from the at least three metallic electrode layers”
Regarding Claim 18, the claim recites “the topmost surface of the layer stack comprises a surface segment which laterally extends between, and is laterally bounded by . . . an entirety of the surface segment of the topmost surface of the layer stack is in contact”. However, claim 18 depends on claim 16 which has previously recited “the first contact assembly is formed entirely within an area of [[said]] a surface segment of the topmost surface of the layer stack” (see objections above). It is therefore unclear if the surface segment of the topmost surface of the layer stack recited in claim 18 is the same surface segment as required by claim 16 or is intended to represent a different surface segment of the topmost surface of the layer stack. For this reason, claim 18 is rejected under 35 U.S.C. 112(b). For the purposes of this examination, claim 18 will be interpreted to read as “the topmost surface of the layer stack comprises a second surface segment which laterally extends between, and is laterally bounded by . . . an entirety of the second surface segment of the topmost surface of the layer stack is in contact”
Regarding Claim 19, the claim recites “the groups of first-type deep trenches” and “the groups of second-type deep trenches” in lines 2 and 4 of the claim. However, claim 19 depends on claim 15 which has not previously recited groups of first-type and second-type deep trenches. However, independent claim 16 has recited these structures and provided details about their characteristics in the overall structure. It is therefore unclear if the recitations of first-type and second-type deep trenches in claim 19 is intended to be a new structure as part of the claim 15 chain, or if claim 19 was intended to be dependent on claim 16 in order to provide proper antecedent basis for “the groups of first-type deep trenches” and “the groups of second-type deep trenches”. For this reason, claim 19 is rejected under 35 U.S.C. 112(b) and claim 20 is rejected under 35 U.S.C. 112(b) at least for its dependencies. For the purposes of this examination, the opening line of claim 19 will be interpreted to read as “The method of Claim [[15]] 16, wherein” to provide proper antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 7-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0061798 A1; Wong et al.; 03/2012; (“Wong”) in view of US 11,063,157 B1; Cheng et al.; 07/2021; (“Cheng”).
Regarding Claim 1. Wong discloses A method of forming a semiconductor structure including a deep trench capacitor (Figures 1-3 and 18-24, formation of a deep trench capacitor structure where Figures 18-24 are a continuation from Figure 3 according to [0067]), comprising:
forming at least one deep trench (#9, Figure 1, deep trench) in a substrate (#10, Figure 1, substrate material layer which #9 is formed in);
forming a layer stack (#20, #30, #40, #50, and #60, Figure 2, stack of layers) including at least three metallic electrode layers (#20, #40, and #60, Figure 2, first, second, and third conductive layers which may be formed of metal material according to [0029]-[0033]) interlaced with at least two node dielectric layers (#30 and #50, Figure 2, first and second node dielectric layers) over the substrate (Figure 2, the layer stack is formed over #10), wherein the layer stack continuously extends into the at least one deep trench (Figure 2, the layer stack extends continuously into all of the trenches);
forming a contact-level dielectric layer (#70, Figure 18, contact level dielectric layer) over the substrate and the layer stack (Figure 18, #70 is formed over the substrate and the stack);
forming contact via cavities (#271, #272, and #273, Figure 22, first, second, and third type via cavities) through the contact-level dielectric layer down to a respective one of the at least three metallic electrode layers (Figures 18-22, #217-#273 are formed through #70 down to a respective one of #20, #40, or #60); and
forming contact assemblies (#291-#293 and #290, Figure 24, first, second, and third type contact via structures and their corresponding dielectric spacers) in the contact via cavities (Figures 22-24, #290-#293 are formed in the respective vias), wherein each of the contact assemblies comprises a respective tubular insulating spacer (Figure 24 and [0073], #290s are tubular dielectric spacers formed by removing the horizontal portions of #290L in Figure 23) and a respective contact via structure that is laterally surrounded by the respective tubular insulating spacer (Figure 24 and [0074], #291-#293 are contact vias which are surrounded laterally at least partially by #290s), and wherein a first contact assembly selected from the contact assemblies comprises a first tubular insulating spacer that is formed directly on a first cylindrical sidewall of [[the]] a second metallic electrode layer of the at least three metallic electrode layers and directly on a first cylindrical sidewall of [[the]] a third metallic electrode layer of the at least three metallic electrode layers ([0039], the vias are described as having a diameter and are thus interpreted to be circular such that the #290s in each via are cylinders with cylindrical sidewalls directly on layers they pass through; #290 in the via of #291 has sidewalls directly on cylindrical surfaces of #40 and #60).
Wong does not disclose a cavity is present in an unfilled volume of the at least one deep trench.
However, Cheng teaches deep trench capacitor structure with the inclusion of a cavity (#103, Figure 2, cavity) in an unfilled volume of the at least one deep trench (Figure 2, #103 is an unfilled volume of the deep trench (#102t) in which the trench capacitor (#106) is located in the substrate (#102).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider including the cavity in an unfilled volume of the trench in Wong, as was done in Cheng, since the cavity “provides space for the electrodes and dielectric layers to expand when exposed to heat. This mitigates force applied to the semiconductor substrate as the aforementioned layers undergo thermal expansion, thereby decreasing warping, breaking, and/or cracking of the semiconductor substrate” (Cheng, column 3, lines 4-9).
Regarding Claim 7. Wong in view of Cheng discloses The method of Claim 1, wherein the tubular insulating spacers are formed by:
conformally depositing an insulating material layer in the contact via cavities (#290L, Figure 23, a dielectric liner is deposited over and into the contact via cavities as a conformal layer according to [0072]); and
anisotropically etching the insulating material layer, wherein remaining tubular portions of the insulating material layer comprise the tubular insulating spacers (Figure 24, [0073], an anisotropic etch process is used to at least partially etch horizontal portions of #290L in order to form the tubular dielectric spacers #290).
Regarding Claim 8. Wong discloses A method of forming a semiconductor structure including a deep trench capacitor (Figures 1-3 and 18-24, formation of a deep trench capacitor structure where Figures 18-24 are a continuation from Figure 3 according to [0067]), comprising:
forming a first deep trench (#9 left most, Figure 1, deep trench) and a second deep trench (#9 second from the left most, Figure 1, deep trench) extending downward from a top surface of a substrate (#10, Figure 1, substrate material layer which #9 is formed in) that is located within a first horizontal plane (Figure 1, let the top surface of #10 be a first horizontal plane);
forming a layer stack (#20, #30, #40, #50, and #60, Figure 2, stack of layers) including at least three metallic electrode layers (#20, #40, and #60, Figure 2, first, second, and third conductive layers which may be formed of metal material according to [0029]-[0033]) interlaced with at least two node dielectric layers (#30 and #50, Figure 2, first and second node dielectric layers), wherein each layer within the layer stack continuously extends over the top surface of the substrate and into each of the first deep trench and the second deep trench (Figure 2, each layer of the stack continuously extends over the top surface of #10 and into each of the deep trenches), wherein the at least three metallic electrode layers comprise a first metallic electrode layer (#20, Figure 2), a second metallic electrode layer (#40, Figure 2), and a third metallic electrode layer (#60, Figure 2) in an order of proximity from the substrate (Figure 2, #20, #40, and #60 are stacked in order from bottom and top resulting in increasing vertical distance from #10), wherein a topmost surface of the layer stack is formed entirely within a second horizontal plane that overlies the first horizontal plane (Figure 2, the topmost surface of the stack being the topmost surface of #60 is a second horizontal plane which overlies the top surface of #10); and
forming a contact-level dielectric layer (#70, Figure 18, contact level dielectric layer) over the substrate and the layer stack (Figure 18, #70 is formed over the substrate and the stack); and
forming a first contact assembly (#291 and #290, Figure 24, contact via structure and its dielectric spacer) through the contact-level dielectric layer (Figure 24, the combination of #291 and #290 passed through #70),
wherein the first contact assembly is formed entirely within an area of [[said]] a surface segment of the topmost surface of the layer stack (Figure 24, the combination of #291 and #290 is formed entirely within an area of a surface segment, the entire upper surface of #60, of the topmost surface of the layer stack), and includes a first tubular insulating spacer (Figure 24 and [0073], #290s are tubular dielectric spacers formed by removing the horizontal portions of #290L in Figure 23) laterally surrounding a first contact via structure (Figure 24 and [0074], #291 is a contact via which is surrounded laterally at least partially by #290) that contacts a horizontal surface of the first metallic electrode layer (Figure 24, #291 contacts a horizontal surface of #20), wherein the first tubular insulating spacer contacts a first cylindrical sidewall of the second metallic electrode layer, and a first cylindrical sidewall of the third metallic electrode layer ([0039], the vias are described as having a diameter and are thus interpreted to be circular such that the #290s in each via are cylinders with cylindrical sidewalls directly on layers they pass through; #290 in the via of #291 has sidewalls directly on cylindrical surfaces of #40 and #60).
Wong does not disclose forming a dielectric fill material layer over the layer stack, wherein the dielectric fill material layer comprises a first horizontally-extending portion that is located within an area of an outer periphery of the topmost surface of the layer stack and is located entirely above the second horizontal plane and laterally extends over entire areas of the first deep trench and the second deep trench, a first vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the first deep trench, and a second vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the second deep trench;
forming the contact-level dielectric layer over the dielectric fill material layer,
forming the first contact assembly through the first horizontally-extending portion of the dielectric fill material layer, and
wherein the first tubular insulating spacer contacts a first cylindrical sidewall of the first horizontally-extending portion of the dielectric fill material layer.
However, Cheng teaches deep trench capacitor structure with the inclusion of a cavity (#103, Figure 2, cavity) in an unfilled volume of the at least one deep trench (Figure 2, #103 is an unfilled volume of the deep trench (#102t) in which the trench capacitor (#106) is located in the substrate (#102), and
forming a dielectric fill material layer (#114 and #116, Figure 2, capping dielectric layer and etch stop layer made of dielectric material according to column 6, lines 33-36) over the layer stack (Figure 2, #114 is formed over the layer stack of the deep trench capacitor), wherein the dielectric fill material layer comprises a first horizontally-extending portion (Figure 2, #114 and #116 have a first horizontally extending portion on the upper surface of the stack) that is located within an area of an outer periphery of the topmost surface of the layer stack and is located entirely above the second horizontal plane and laterally extends over entire areas of the first deep trench and the second deep trench (Figure 2, the topmost portions of #114 and #116 are entirely within an areas of the topmost layer of the stack and are entirely above the second horizontal plane of the top surface of the stack and laterally extend over the entire area of the first and second deep trenches), a first vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the first deep trench (Figure 2, #114 includes a vertically extending portion that extends into the central cavity of the left deep trench from the horizontally extending portion), and a second vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the second deep trench (Figure 2, #114 includes a vertically extending portion that extends into the central cavity of the right deep trench from the horizontally extending portion);
forming the contact-level dielectric layer over the dielectric fill material layer (#122, Figure 2, interconnect dielectric structure that is formed over #114 and #116),
forming the first contact assembly through the first horizontally-extending portion of the dielectric fill material layer (#118, Figure 2, a conductive via passes through the top horizontally extending portion of #114 and #116).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the dielectric fill material extending into an underlying cavity in the trench from Cheng in the device of Wong, such that the dielectric spacers of Wong also contact a cylindrical sidewall of the horizontal portion of the dielectric fill material as the contacts pass through all upper layers, since the cavity “provides space for the electrodes and dielectric layers to expand when exposed to heat. This mitigates force applied to the semiconductor substrate as the aforementioned layers undergo thermal expansion, thereby decreasing warping, breaking, and/or cracking of the semiconductor substrate” (Cheng, column 3, lines 4-9) and the dielectric fill material seals the cavity to maintain pressure and cavity integrity (Cheng, column 6, lines 21-31).
Regarding Claim 9. Wong in view of Cheng discloses The method of Claim 8, further comprising forming a second contact assembly (Wong, #293 and #290, Figure 24, contact via structure and its dielectric spacer) through the contact-level dielectric layer (Wong, Figure 24, the combination of #293 and #290 passed through #70) and the first horizontally-extending portion of the dielectric fill material layer (Wong in view of Cheng, forming #114 and #116 from Figure 2 of Cheng over the entire upper surface of the layer stack in Figure 24 of Wong would necessarily result in #293/#290 passing through the horizontally extending portion of #114 and #116), wherein the second contact assembly is formed entirely within the area of said surface segment of the topmost surface of the layer stack (Wong, Figure 24, the combination of #293/#290 is formed entirely within the upper surface of #60), and includes a second tubular insulating spacer laterally surrounding a second contact via structure (Figure 24 and [0074], #293 is a contact via which is surrounded laterally at least partially by #290) that contacts a horizontal surface of the third metallic electrode layer (Figure 24, #293 contacts a horizontal surface of #60), wherein the second tubular insulating spacer contacts a second cylindrical sidewall of the first horizontally-extending portion of the dielectric fill material layer (Wong in view of Cheng, forming #114 and #116 from Figure 2 of Cheng over the entire upper surface of the layer stack in Figure 24 of Wong would necessarily result in #290 passing through and contacting a cylindrical sidewall of the horizontally extending portions of #114 and #116).
Regarding Claim 10. Wong in view of Cheng discloses The method of Claim 9, further comprising forming a first metal pad structure comprising a bottom surface on a top surface of the first contact via structure and on a top surface of the second contact via structure (Wong, [0075], a metal interconnect structure may be provided in a not shown overlying interconnect level dielectric layer to connect the vias for #20 and #60 such that its bottom surface would necessarily contact top surfaces of the respective vias).
Regarding Claim 11. Wong in view of Cheng discloses The method of Claim 9, further comprising forming a third contact assembly (Wong, #292 and #290, Figure 24, contact via structure and its dielectric spacer) entirely within the area of said surface segment of the topmost surface of the layer stack (Wong, Figure 24, the combination of #292/#290 is formed entirely within the upper surface of #60), wherein the third contact assembly includes a third tubular insulating spacer laterally surrounding a third contact via structure (Figure 24 and [0074], #292 is a contact via which is surrounded laterally at least partially by #290) that contacts a horizontal surface of the second metallic electrode layer (Figure 24, #292 contacts a horizontal surface of #40), wherein the third tubular insulating spacer is formed on a second cylindrical sidewall of the third metallic electrode layer ([0039], the vias are described as having a diameter and are thus interpreted to be circular such that the #290s in each via are cylinders with cylindrical sidewalls directly on layers they pass through; #290 in the via of #292 has sidewalls directly on cylindrical surfaces of #60).
Regarding Claim 12. Wong in view of Cheng discloses The method of Claim 11, wherein the first cylindrical sidewall of the third metallic electrode layer and the second cylindrical sidewall of the third metallic electrode layer are formed within a horizontally-extending portion of the third metallic electrode layer (Wong, Figure 24, the cylindrical sidewalls of #60 for both contact vias including #292 and #291 are formed within the top horizontally extending portion of #60), and are vertically spaced from the substrate by a same vertical distance (Wong, Figure 24, the two cylindrical sidewalls of #60 passed through by #292 and #291 are spaced from #10 by the same vertical distance).
Regarding Claim 13. Wong in view of Cheng discloses The method of Claim 8, wherein an entirety of the surface segment of the topmost surface of the layer stack is in contact with the first horizontally-extending portion of the dielectric fill material layer within the second horizontal plane (Cheng, Figure 2, an entirety of the topmost surface of the layer stack, i.e. an entirety of the uppermost surface of #112d, is in direct contact with the horizontally extending portion of #114).
Regarding Claim 14. Wong in view of Cheng discloses The method of Claim 8, wherein the dielectric fill material layer (Cheng, Figure 2, #114 and #116) comprises a second horizontally-extending portion that is located outside a region in which the layer stack is present (Cheng, Figure 2, #116 includes a second horizontally extending portion all the way to the left of the figure and present outside of the region in which the stack of #112s and #110s, which form the capacitor, are located) and vertically recessed relative to the first horizontally-extending portion (Cheng, Figure 2, the portion of #116 which is all the way to the left of the figure is vertically recessed relative to the topmost portion which extends over the top of the stack).
Regarding Claim 15. Wong in view of Cheng discloses The method of Claim 9, further comprising, wherein the contact-level dielectric layer (Cheng, Figure 2, #122) has a horizontal top surface that extends over the first horizontally-extending portion and [[the]] a second horizontally-extending portion of the dielectric fill material layer (Figure 2, #122 has a horizontal top surface that extends over the entirety of #114 and #116 such that it extends over all horizontally-extending segments).
Claim(s) 2-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0061798 A1; Wong et al.; 03/2012; (“Wong”) in view of US 11,063,157 B1; Cheng et al.; 07/2021; (“Cheng”), as applied to claim 1, and further in view of US 2015/0145103 A1; Chou et al.; 05/2015; (“Chou”).
Regarding Claim 2. Wong in view of Cheng discloses The method of Claim 1, further comprising:
forming via cavities (Wong, #271-#273, Figure 19, first, second, and third type via cavities formed prior to extension through the electrode layers) having a same depth through the contact-level dielectric layer (Wong, Figure 19, #271-#273 all have the same depth through #70); and
selectively vertically extending the via cavities by different vertical extension distances, whereby the contact via cavities are formed (Wong, Figures 19-22, #271-#273 are selectively extended by different vertical distances to form the cavities extending to their respective electrode layers).
Wong in view of Cheng do not disclose forming a dielectric hard mask layer over the contact-level dielectric layer; and forming via cavities having a same depth through the dielectric hard mask layer and the contact-level dielectric layer.
However, Chou teaches a method of forming a deep trench capacitor structure (Figures 4A-4I) including forming a contact level dielectric (#130, Figure 4E, cap dielectric layer) over a stack structure (#120a-c, Figure 4E) and forming a dielectric hard mask layer over the contact-level dielectric layer ([0059]-[0060], a patterned mask is used to define the plurality of contact holes prior to subsequent etching processes); and forming via cavities having a same depth through the dielectric hard mask layer and the contact-level dielectric layer (Figure 4F, [0059]-[0060], #402, #404, #406, and #408 are formed to the same depth through #130 and necessarily through the hard mask with the depth being fully through the respective structures).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider additionally forming the mask structure of Chou on the device of Wong in view of Cheng since the mask structure may help to protect underlying structures from damage during subsequent etching processes through the selective etching of the contact level dielectric and the mask layer and help to ensure final intended etching depth (see [0061] of Chou).
Regarding Claim 3. Wong in view of Cheng and Chou discloses The method of Claim 2, further comprising:
applying a photoresist layer (Wong, #277, Figure 20, second photoresist layer) over the dielectric hard mask layer after formation of the via cavities (Wong, Figure 20, #277 is formed after formation of the via cavities formed in Figure 19 and is necessarily formed over the mask provided by Chou to protect underlying structure during etching);
patterning the photoresist layer so that patterned portions of the photoresist layer does not cover a first subset of the via cavities and covers a second subset of the via cavities (Wong, Figure 30, #277 is formed to not cover via cavities #271 and #272 and is formed to cover via cavities #273);
vertically extending the first subset of the via cavities through two metallic electrode layers selected from the at least three metallic electrode layers (Wong, Figure 21, at least one #271 is vertically extended through #20 and #40); and
removing the photoresist layer (Wong, Figure 21, [0069], #277 is removed).
Regarding Claim 4. Wong in view of Cheng and Chou discloses The method of Claim 3, further comprising:
applying an additional photoresist layer (#279, Figure 21, third photoresist layer) over the dielectric hard mask layer after removal of the photoresist layer (Wong, Figure 21, #279 is formed after removal of #277 and is necessarily formed over the mask provided by Chou to protect underlying structure during etching); and
patterning the additional photoresist layer so that patterned portions of the additional photoresist layer [[does]] do not cover a first via cavity selected from the first subset of the via cavities and covers a second via cavity selected from the first subset of the via cavities (Wong, Figure 21, #279 is patterned so that remaining portions do not cover #271s and do cover #272s).
Regarding Claim 5. Wong in view of Cheng and Chou discloses The method of Claim 4, further comprising:
vertically extending the first via cavity through another metallic electrode [[layers]] layer selected from the at least three metallic electrode layers (Wong, Figure 21, at least one #271 is vertically extended further through #40 after removal of the first photoresist); and
removing the additional photoresist layer, whereby the contact via cavities are provided (Wong, Figure 22, [0071], #279 is removed).
Regarding Claim 6. Wong in view of Cheng and Chou discloses The method of Claim 3, wherein vertically extending the first subset of the via cavities through the two metallic electrode layers selected from the at least three metallic electrode layers comprises anisotropically etching a material of the two metallic electrode layers selective to a dielectric material of the dielectric hard mask layer (Wong, [0068]-[0071], anisotropic etching processes such as reactive ion etch processes are used to extend the contact vias selective to the photoresist and overlying dielectric layers).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0061798 A1; Wong et al.; 03/2012; (“Wong”) in view of US 11,063,157 B1; Cheng et al.; 07/2021; (“Cheng”) and US 2013/0161792 A1; Tran et al.; 06/2013; (“Tran”).
Regarding Claim 16. Wong discloses A method of forming a semiconductor structure including a deep trench capacitor (Figures 1-3 and 18-24, formation of a deep trench capacitor structure where Figures 18-24 are a continuation from Figure 3 according to [0067]), comprising:
forming a plurality of deep trenches (#9s, Figure 1, plurality of deep trenches) extending downward from a top surface of a substrate (#10, Figure 1, substrate material layer which #9s are formed in and extend downwards into) that is located within a first horizontal plane (Figure 1, let the top surface of #10 be a first horizontal plane), wherein the plurality of deep trenches comprises groups of first-type deep trenches (Figure 1, left two #9s), and further comprises groups of second-type deep trenches (Figure 1, right two #9s);
forming a layer stack (#20, #30, #40, #50, and #60, Figure 2, stack of layers) including at least three metallic electrode layers (#20, #40, and #60, Figure 2, first, second, and third conductive layers which may be formed of metal material according to [0029]-[0033]) interlaced with at least two node dielectric layers (#30 and #50, Figure 2, first and second node dielectric layers), wherein each layer within the layer stack continuously extends over the top surface of the substrate and into each of the first-type deep trench and the second-type deep trench (Figure 2, each layer of the stack continuously extends over the top surface of #10 and into each of the deep trenches), wherein the at least three metallic electrode layers comprise a first metallic electrode layer (#20, Figure 2), a second metallic electrode layer (#40, Figure 2), and a third metallic electrode layer (#60, Figure 2) in an order of proximity from the substrate (Figure 2, #20, #40, and #60 are stacked in order from bottom and top resulting in increasing vertical distance from #10), wherein a topmost surface of the layer stack is located entirely within a second horizontal plane that overlies the first horizontal plane (Figure 2, the topmost surface of the stack being the topmost surface of #60 is a second horizontal plane which overlies the top surface of #10); and
forming a contact-level dielectric layer (#70, Figure 18, contact level dielectric layer) over the substrate and the layer stack (Figure 18, #70 is formed over the substrate and the stack); and
forming a first contact assembly (#291 and #290, Figure 24, contact via structure and its dielectric spacer) through the contact-level dielectric layer (Figure 24, the combination of #291 and #290 passed through #70),
wherein the first contact assembly is formed entirely within an area of [[said]] a surface segment of the topmost surface of the layer stack (Figure 24, the combination of #291 and #290 is formed entirely within an area of a surface segment, the entire upper surface of #60, of the topmost surface of the layer stack), and includes a first tubular insulating spacer (Figure 24 and [0073], #290s are tubular dielectric spacers formed by removing the horizontal portions of #290L in Figure 23) laterally surrounding a first contact via structure (Figure 24 and [0074], #291 is a contact via which is surrounded laterally at least partially by #290) that contacts a horizontal surface of the first metallic electrode layer (Figure 24, #291 contacts a horizontal surface of #20), wherein the first tubular insulating spacer contacts a first cylindrical sidewall of the second metallic electrode layer, and a first cylindrical sidewall of the third metallic electrode layer ([0039], the vias are described as having a diameter and are thus interpreted to be circular such that the #290s in each via are cylinders with cylindrical sidewalls directly on layers they pass through; #290 in the via of #291 has sidewalls directly on cylindrical surfaces of #40 and #60).
Wong does not disclose forming a dielectric fill material layer over the layer stack, wherein the dielectric fill material layer comprises a first horizontally-extending portion that is located within an area of an outer periphery of the topmost surface of the layer stack and is located entirely above the second horizontal plane and laterally extends over entire areas of the first deep trench and the second deep trench, a first vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the first deep trench, and a second vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the second deep trench;
forming the contact-level dielectric layer over the dielectric fill material layer,
forming the first contact assembly through the first horizontally-extending portion of the dielectric fill material layer, and
wherein the first tubular insulating spacer contacts a first cylindrical sidewall of the first horizontally-extending portion of the dielectric fill material layer; and
the plurality of deep trenches comprises the groups of first-type deep trenches each having a greater first lateral extent along a first horizontal direction than along a second horizontal direction, and further comprises the groups of second-type deep trenches each having a greater second lateral extent along the second horizontal direction than along the first horizontal direction, wherein the plurality of deep trenches comprises a neighboring pair of deep trenches that includes a first deep trench and a second deep trench without any intervening deep trench therebetween.
However, Cheng teaches deep trench capacitor structure with the inclusion of a cavity (#103, Figure 2, cavity) in an unfilled volume of the at least one deep trench (Figure 2, #103 is an unfilled volume of the deep trench (#102t) in which the trench capacitor (#106) is located in the substrate (#102), and
forming a dielectric fill material layer (#114 and #116, Figure 2, capping dielectric layer and etch stop layer made of dielectric material according to column 6, lines 33-36) over the layer stack (Figure 2, #114 is formed over the layer stack of the deep trench capacitor), wherein the dielectric fill material layer comprises a first horizontally-extending portion (Figure 2, #114 and #116 have a first horizontally extending portion on the upper surface of the stack) that is located within an area of an outer periphery of the topmost surface of the layer stack and is located entirely above the second horizontal plane and laterally extends over entire areas of the first deep trench and the second deep trench (Figure 2, the topmost portions of #114 and #116 are entirely within an areas of the topmost layer of the stack and are entirely above the second horizontal plane of the top surface of the stack and laterally extend over the entire area of the first and second deep trenches), a first vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the first deep trench (Figure 2, #114 includes a vertically extending portion that extends into the central cavity of the left deep trench from the horizontally extending portion), and a second vertically-extending portion that vertically extends from the first horizontally-extending portion into a central volume of the second deep trench (Figure 2, #114 includes a vertically extending portion that extends into the central cavity of the right deep trench from the horizontally extending portion);
forming the contact-level dielectric layer over the dielectric fill material layer (#122, Figure 2, interconnect dielectric structure that is formed over #114 and #116),
forming the first contact assembly through the first horizontally-extending portion of the dielectric fill material layer (#118, Figure 2, a conductive via passes through the top horizontally extending portion of #114 and #116).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide the dielectric fill material extending into an underlying cavity in the trench from Cheng in the device of Wong, such that the dielectric spacers of Wong also contact a cylindrical sidewall of the horizontal portion of the dielectric fill material as the contacts pass through all upper layers, since the cavity “provides space for the electrodes and dielectric layers to expand when exposed to heat. This mitigates force applied to the semiconductor substrate as the aforementioned layers undergo thermal expansion, thereby decreasing warping, breaking, and/or cracking of the semiconductor substrate” (Cheng, column 3, lines 4-9) and the dielectric fill material seals the cavity to maintain pressure and cavity integrity (Cheng, column 6, lines 21-31).
Wong in view of Cheng do not disclose the plurality of deep trenches comprises the groups of first-type deep trenches each having a greater first lateral extent along a first horizontal direction than along a second horizontal direction, and further comprises the groups of second-type deep trenches each having a greater second lateral extent along the second horizontal direction than along the first horizontal direction, wherein the plurality of deep trenches comprises a neighboring pair of deep trenches that includes a first deep trench and a second deep trench without any intervening deep trench therebetween.
However, Tran teaches a plurality of deep trench capacitors (Figure 1C; [0027], trench capacitors #108) comprising groups of first deep trench capacitors (#138A, Figure 1C; [0027], first capacitor region) each having a greater first lateral extent along a first horizontal direction than along a second horizontal direction (the trenches/capacitors of #138A are observed in Figure 1C to have a greater lateral extent in a top to bottom direction than in a left to right direction), and further comprising groups of second deep trench capacitors (#138B, Figure 1C; [0027], second capacitor region) each having a greater second lateral extent along the second horizontal direction than along the first horizontal direction (the trenches/capacitors of #138A are observed in Figure 1C to have a greater lateral extent in the left to right direction than in the top to bottom direction), wherein the plurality of deep trenches comprises a neighboring pair of deep trenches that includes a first deep trench and a second deep trench without any intervening deep trench therebetween (Figure 1C, in the top left #138A, the rightmost deep trench neighbors any of the deep trenches in the adjacent #138B without any intervening deep trenches).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to utilize the trench capacitor layout of Tran to distribute the plurality of trench capacitors in Wong in view of Cheng in order to facilitate stress management on the substrate by reducing warpage and thus increase the fraction of the substrate usable for other devices as described in [0027] of Tran.
Regarding Claim 17. Wong in view of Cheng and Tran discloses The method of Claim 16, further comprising forming a second contact assembly (Wong, #293 and #290, Figure 24, contact via structure and its dielectric spacer) through the contact-level dielectric layer (Wong, Figure 24, the combination of #293 and #290 passed through #70) and the first horizontally-extending portion of the dielectric fill material layer (Wong in view of Cheng, forming #114 and #116 from Figure 2 of Cheng over the entire upper surface of the layer stack in Figure 24 of Wong would necessarily result in #293/#290 passing through the horizontally extending portion of #114 and #116), wherein the second contact assembly is formed entirely within the area of said surface segment of the topmost surface of the layer stack (Wong, Figure 24, the combination of #293/#290 is formed entirely within the upper surface of #60), and includes a second tubular insulating spacer laterally surrounding a second contact via structure (Figure 24 and [0074], #293 is a contact via which is surrounded laterally at least partially by #290) that contacts a horizontal surface of the third metallic electrode layer (Figure 24, #293 contacts a horizontal surface of #60), wherein the second tubular insulating spacer contacts a second cylindrical sidewall of the first horizontally-extending portion of the dielectric fill material layer (Wong in view of Cheng, forming #114 and #116 from Figure 2 of Cheng over the entire upper surface of the layer stack in Figure 24 of Wong would necessarily result in #290 passing through and contacting a cylindrical sidewall of the horizontally extending portions of #114 and #116).
Regarding Claim 18. Wong in view of Cheng and Tran discloses The method of Claim 16, wherein:
the topmost surface of the layer stack comprises a second surface segment (Wong, Figure 24, let the first surface segment be the region in which #291 is formed and let the second surface segment be the portion of the top surface of the stack in which #292 is formed) which laterally extends between, and is laterally bounded by, a top edge of the first vertically-extending portion of the dielectric fill material layer and a top edge of the second vertically-extending portion of the dielectric fill material layer and located entirely within the second horizontal plane (Wong in view of Cheng, Figure 24 of Wong and Figure 2 of Cheng, forming the dielectric fill of Cheng to extend vertically into the two adjacent trenches would necessarily result in the second (middle) surface segment of the top of the stack where #292 is formed being bounded laterally be the two vertically extending portions and the second (middle) surface segment is entirely within the second horizontal plane); and
an entirety of the second surface segment of the topmost surface of the layer stack is in contact with the first horizontally-extending portion of the dielectric fill material layer within the second horizontal plane (Cheng, Figure 2, an entirety of the topmost surface of the layer stack, i.e. an entirety of the uppermost surface of #112d, is in direct contact with the horizontally extending portion of #114).
Regarding Claim 19. Wong in view of Cheng and Tran discloses The method of Claim [[15]] 16, wherein:
the groups of first-type deep trenches are arranged in a pattern of a first two-dimensional array (Tran, #138A, Figure 1C, the first capacitor region is arranged as a two-dimensional array of trench capacitors #108);
the groups of second-type deep trenches are arranged in a pattern of a second two-dimensional array (Tran, #138B, Figure 1C, the second capacitor region is arranged as a two-dimensional array of trench capacitors #108); and
the second two-dimensional array is interlaced with the first two-dimensional array (Tran, Figure 1C, the two capacitor region arrays of #138A and #138B are interlaced with each other).
Regarding Claim 20. Wong in view of Cheng and Tran discloses The method of Claim 19, wherein:
each neighboring pair of groups of first-type deep trenches is laterally spaced from each other by a respective group of second deep trenches (Tran, Figure 1C, each neighboring pair of regions #138A is laterally separated by a region #138B); and
each neighboring pair of groups of second-type deep trenches is laterally spaced from each other by a respective group of first deep trenches (Tran, Figure 1C, each neighboring pair of regions #138B is laterally separated by a region #138A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2017/0104057 A1; Voiron, Frédéric; 04/2017 – Figures 1-3 disclose a three electrode (#16, #20, and #24) deep trench capacitor structure with overlying contact electrodes (#40 and #42) passing through the various electrode layers and interlaced dielectrics (#18 and #22) and an upper dielectric layer (#26) and interlevel dielectric structure (#38) to reach corresponding electrode layers.
US 2020/0005999 A1; Masuda et al.; 01/2020 – Figures 12-14 and 5-6 disclose a method of making a multi electrode with interleaved dielectrics (#20) deep trench capacitor structure with overlying contact electrodes (#2 and #3) passing through the various electrode layers and interlaced dielectrics and an upper dielectric layer (#30) and interlevel dielectric structure (#40) to reach corresponding electrode layers.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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