DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II Claim 17-20 in the reply filed on 07/16/2026 is acknowledged. Claims 1-16 have been cancelled as being drawn to a non-elected group of invention. Claims 21-36 have been added. Claims 17-36 are pending in this application. For the purpose of examination of the present application, claims 17-36 have been examined.
Information disclosure
Information disclosure statement has not been received. If applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over. Lin et al (US20220352379A1) in view of Huang et al (US20220285519A1).
Re claim 17 Lin teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (220, fig 6) [0071] on a substrate (10, fig 6) [0069];
forming a gate dielectric layer (240, fig 6) [0073] on the gate electrode [0071];
forming a channel (250, fig 6) [0083] disposed on the gate dielectric layer (240, fig 6) opposite (top of 240) to the gate electrode (220, fig 6); and
forming a drain unit (277/291, fig 6) [0091-0092] and a source unit (276/290, fig 6) [0091-0092] on the gate dielectric layer (240, fig 6) [0092], the drain unit (291, fig 6) [0092] and the source unit (290, fig 6) being connected to the channel (250, fig 6) 0083] and spaced apart from each other by the channel (source/ drain structures are positioned at separate locations along the channel layer with an intervening portion of the channel layer extending between the source and drain structures) (250, fig 6)[0091],
at least one of the drain unit (277/291 fig 6) and the source unit (276/290, fig 6) including an electrode (291/290, fig 6) [0091-0092].
Lin does not teach a tunnel layer disposed between the electrode and the channel so as to adjust a barrier height between the electrode and the channel.
Huang teaches a tunnel layer (114, fig 1) [0021] disposed between the electrode (118, fig 1) and the channel (110, fig 1) [0021] so as to adjust a barrier height between the electrode (118, fig 1) and the channel (110, fig 1) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Lin to include a tunnel layer disposed between the electrode and the channel so as to adjust a barrier height between the electrode and the channel as claimed.
The ordinary artisan would have been motivated to modify Lin based on the teaching of Huang in the above manner for the purpose of reducing the power consumption of the IC chip [0071]
Re claim 18 Lin in view of Huang teaches the method according to claim 17, further comprising forming a cap layer (260, fig 6) [Lin, 0088] on the channel (250, fig 6) [Lin, 0088].
Re claim 19 Lin in view of Huang teaches the method according to claim 18, further comprising forming a first interface layer (230, fig 6) [Lin, 0099] between the gate electrode (220, fig 6) [Lin, 0071] and the gate dielectric layer (240, fig 6) [Lin, 0099].
Re claim 20 Lin in view of Huang teaches the method according to claim 19, further comprising forming a second interface layer (245, fig 6) [0079] between the channel (250, fig 6) and the gate dielectric layer (240, fig 6) [Lin, 0051].
Re claim 31 Lin in view of Huang teaches a method for manufacturing a semiconductor structure (fig 6), comprising: forming a gate electrode (220, fig 5A-6) [0068] on a substrate (10, fig 6) [0068];
forming a gate dielectric layer (240, fig 5B) [0051] on the gate electrode (220, fig 5B-6);
forming a laminate (245/250, fig 5G) [0083] on the gate dielectric layer (240, fig 5B) opposite to the gate electrode, the laminate (245/250, fig 5G) including a channel (250, fig 5B) [0083];
depositing a dielectric layer (260, fig 5G) [0088] on the gate dielectric layer (240, fig 5G) to cover the laminate (245/250, fig 5G);
patterning the dielectric layer (260, fig 5H) [0090] to form a first opening (274, fig 5G, 5H) and a second opening (273, fig 5G) in the dielectric layer (260, fig 5H), such that two opposite side surfaces (right/left surfaces, 277/277, fig 5H) of the channel (250, fig 5G) are respectively exposed from the first opening (274, fig 5H) and the second opening (273, fig 5H) [0090], and
forming a drain unit (274/291) and a source unit (273/290) in the first opening (274, fig 5H) and the second opening (273, fig 5H), respectively,
the drain unit (277/291, fig 5I) and the source unit (276/290, fig 5I) being connected to the channel (250, fig 5I) and spaced apart from each other by the channel (250, fig 6).
Lin does not teach at least one of the drain unit and the source unit including an electrode and a tunnel layer disposed between the electrode and the channel so as to adjust a barrier height between the electrode and the channel.
Huang does teach a tunnel layer (114, fig 1) [0021] disposed between the electrode (118, fig 1) and the channel (110, fig 1) [0021] so as to adjust a barrier height between the electrode (118, fig 1) and the channel (110, fig 1) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Lin to include a tunnel layer disposed between the electrode and the channel so as to adjust a barrier height between the electrode and the channel as claimed.
The ordinary artisan would have been motivated to modify Lin based on the teaching of Huang in the above manner for the purpose of reducing the power consumption of the IC chip [0071].
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US20220352379A1) modified by Huang et al (US20220285519A1) as applied to claim 17 and further in view of Bu et al (US20170018463A1).
Re claim 21 Lin in view of Huang teaches the method according to claim 17,
Lin and Huang do not teach the at least one of the drain unit and the source unit is formed to further include a conductive metal oxide layer disposed between the channel and the tunnel layer.
Bu teaches the at least one of the drain unit and the source unit (152/1110/1010, fig 12B) [0057] is formed to further include a conductive metal oxide layer (920, fig 12B) [0057] disposed between the channel (channel between 152 and 153) and the tunnel layer (910, fig 12B) [0057].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Bu into the structure of Lin and Huang to include the at least one of the drain unit and the source unit is formed to further include a conductive metal oxide layer disposed between the channel and the tunnel layer as claimed.
The ordinary artisan would have been motivated to modify Lin and Huang based on the teaching of Bu in the above manner for the purpose of improving contact resistance [0033].
Re claim 22 Lin in view of Huang and Bu teaches the method according to claim 21, wherein the at least one of the drain unit (153, fig 12B) [0040] and the source unit (152, fig 12B) [0040] is formed to further include a diffusion blocking layer (1010, fig 12B) [0058] disposed between the electrode (1110, fig 12B) [Bu, 0059] and the tunnel layer (0910, fig 12B).
Claims 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lin modified by Huang and Bu as applied to claims 17 and 21 above, and further in view of Onuki et al (US20220328486A1).
Re claim 23 Lin in view of Huang and Bu teach the method according to claim 21, Lin, Huang and Bu do not teach the at least one of the drain unit and the source unit is formed to further include a diffusion blocking layer disposed between the tunnel layer and the conductive metal oxide layer.
Onuki teaches the at least one of the drain unit and the source unit is formed to further include a diffusion blocking layer disposed between the tunnel layer and the conductive metal oxide layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Onuki into the structure of Lin, Huang and Bu to include the at least one of the drain unit and the source unit is formed to further include a diffusion blocking layer (230d, fig 16B)[0392] disposed between the tunnel layer (230a, fig 16B) and the conductive metal oxide layer (250, fig 16B) as claimed.
The ordinary artisan would have been motivated to modify Lin, Huang and Bu in the above manner for the purpose of improving the reliability of the device [0313].
Re claim 24 Lin in view of Huang and Onuki teaches the method according to claim 22, wherein the at least one of the drain unit and the source unit is formed to further include a third interface layer (230b, fig 16B) [Onuki, 0392] disposed between the tunnel layer (230a, fig 6B) [Onuki, 0392] and the conductive metal oxide layer (250, fig 16B) [Onuki 0392].
Re claim 25 Lin in view of Huang and Onuki teaches the method according to claim 24, wherein the at least one of the drain unit and the source unit is formed to further include a fourth interface layer (230c, fig 16B) [Onuki, 0393] disposed between the tunnel layer (230a, fig16B) and the diffusion blocking layer (230d. fig 16B) [Onuki 0393].
Re claim 26 Lin in view of Huang teach the method according to claim 17,
Lin and Huang do not teach the at least one of the drain unit and the source unit is formed to further include a conductive metal oxide layer disposed between the electrode and the tunnel layer.
Onuki teaches the at least one of the drain unit and the source unit is formed to further include a conductive metal oxide layer (230d, fig 10B) [0395] disposed between the electrode (260b, fig 2) [0340] and the tunnel layer (230C, fig 2) [0393].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Onuki into the structure of Lin and Huang to include the at least one of the drain unit and the source unit is formed to further include a conductive metal oxide layer disposed between the electrode and the tunnel layer as claimed.
The ordinary artisan would have been motivated to modify Lin and Huang based on the teaching of Onuki in the above manner for the purpose of improving the reliability of the device [0313].
Re claim 27 Lin in view of Huang teaches the method according to claim 26, wherein the at least one of the drain unit and the source unit is formed to further include a diffusion blocking layer (250, fig 10B) [Onuki, 0398] disposed between the electrode (260b, fig 10B) [Onuki, 0340] and the conductive metal oxide layer (230d, fig 10B) [Onuki, 0397].
Re claim 28 Lin in view of Huang teaches the method according to claim 17, wherein the tunnel layer includes titanium oxide, hafnium oxide, zirconium oxide, gallium oxide, aluminum oxide, silicon oxide, or combinations thereof. (Gallium-Zinc-Oxide (SnIGZO) [Huang, 0032].
Re claim 29 Lin in view of Huang teaches the method according to claim 18, wherein the cap layer (260, fig 6) [Lin, 0088] includes aluminum oxide, silicon oxide (silicon oxide), or a combination thereof.
Re claim 30 Lin in view of Huang teaches the method according to claim 19, wherein the first interface layer (235, fig 6) [Lin 0103] includes titanium oxide, hafnium oxide, zirconium oxide (ZrO2) [Lin 0103], niobium oxide, cerium oxide, or combinations thereof.
Claims 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US20220352379A1) modified by Huang as applied to claims 17 and 31 and further in view Wu et al (US20200258777A1).
Re claim 32 Lin in view of Huang teaches the method according to claim 31,
Lin and Huang do not teach the laminate is formed to further include a cap layer on the channel opposite to the gate dielectric layer, and two opposite side surfaces of the cap layer are respectively exposed from the first opening and the second opening.
Wu teaches the laminate (170/120/140, fig 1) is formed to further include a cap layer (160, fig 1) on the channel (140/120, fig 1) [0023] opposite to the gate dielectric layer (172, fig 1) [0025], and two opposite side surfaces of the cap layer (160, fig 2A) are respectively exposed from the first opening (left 220, fig 1) and the second opening (right 220, fig 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Lin and Huang to include the laminate is formed to further include a cap layer on the channel opposite to the gate dielectric layer, and two opposite side surfaces of the cap layer are respectively exposed from the first opening and the second opening as claimed.
The ordinary artisan would have been motivated to modify Lin and Huang based on the teaching of Wu in the above manner for the purpose of improving the performance of an electrical circuit that uses the electronic devices in its electrical design [0015].
Re claim 33 Lin in view of Huang and Wu teaches the method according to claim 32, wherein the laminate is formed to further include a first interface layer (200, fig 2A) [0035] on the channel (140/120, fig 2A) opposite to the cap layer (160, 2A) [Wu, 0024](left /right) and two opposite side surfaces of the first interface layer (200, fig 2A) are respectively exposed from the first opening (left 220, fig 2A) and the second opening (right 220, fig 2A).
Re claim 34 Lin in view of Huang and Wu teaches the method according to claim 33, further comprising forming a second interface layer (235, fig 6) [Lin, 0102] between the gate electrode (220, fig 6) [Lin, 0071] and the gate dielectric layer (240, fig 6) [Lin, 0102].
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over. Lin et al (US20220352379A1) in view of Huang et al (US20220285519A1) and Wu et al (US20200258777A1).
Re claim 35 Lin teaches a method for manufacturing a semiconductor structure, comprising: forming a gate electrode (220, fig 6) [0071] on a substrate (10, fig 6) [0068];
forming a gate dielectric layer (240, fig 6) [0051] on the gate electrode (220, fig 6) [0071];
forming a channel (250, fig 6) [0083] disposed on the gate dielectric layer (240, fig 6) [0083] opposite to the gate electrode (top of 220); and
forming a drain unit (277/291, fig 6) [0091]and a source unit (276/290, fig 6) [0091] on the gate dielectric layer (240, fig 6) [0073] the drain unit (277/291, fig 6) and the source unit (276/290, fig 6) [0090] being connected to the channel (250, fig 6) and spaced apart from each other by the channel (250, fig 6) [0090],
wherein one of the drain unit and the source unit (276/290, fig 6) includes a first electrode (290, fig 6) and
the other one of the drain unit (277/291, fig 6) [0090] and the source unit includes a second electrode (291, fig 6).
Lin does not teach a first tunnel layer disposed between the first electrode and the channel so as to adjust a first barrier height between the first electrode and the channel, and a second tunnel layer disposed between the second electrode and the channel so as to adjust a second barrier height between the second electrode and the channel, and
Huang teaches a first tunnel layer (left 114, fig 1) disposed between the first electrode (left 118, fig 1) [0021] and the channel (110, fig 1) [0021] so as to adjust a first barrier height between the first electrode (left 118, fig 1) and the channel (110, fig 1) [0021], and a second tunnel layer (right 114, fig 1) disposed between the second electrode (right 118, fig1) and the channel (110, fig1) so as to adjust a second barrier height between the second electrode (right 118, fig 1) and the channel 110, fig 1) [0020-0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Lin to include a first tunnel layer disposed between the first electrode and the channel so as to adjust a first barrier height between the first electrode and the channel, and a second tunnel layer disposed between the second electrode and the channel so as to adjust a second barrier height between the second electrode and the channel as claimed.
The ordinary artisan would have been motivated to modify Lin based on the teaching of Huang in the above manner for the purpose of reducing the power consumption of the IC chip [0071].
Lin and Huang do not teach an interface layer disposed between second electrode and the second tunnel layer.
Wu teaches interface layer (500, fig 2F) [0041] disposed between second electrode (right 700, fig 2F) [0056]and the second tunnel layer (410, fig 2F).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wu into the structure of Lin and Huang to include an interface layer disposed between second electrode and the second tunnel layer as claimed.
The ordinary artisan would have been motivated to modify Lin and Huang based on the teaching of Wu in the above manner for the purpose of increasing production yields. [0065].
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Lin modified by Huang and Wu as applied to claim 35, and further in view of Chang et al (US20210159338A1).
Re claim 36 Lin in view of Huang and Wu teaches the method according to claim 35, wherein
Lin, Huang and Wu do not teach the one of the drain unit and the source unit is formed after forming the other one of the drain unit and the source unit.
Chang teaches the one of the drain unit and the source unit (321, fig 1C-1D) [0020] is formed after forming the other one of the drain unit and the source unit (80, fig 1F) [0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Chang into the structure of Lin, Huang and Wu to include the one of the drain unit and the source unit is formed after forming the other one of the drain unit and the source unit as claimed.
The ordinary artisan would have been motivated to modify Lin, Huang and Wu based on the teaching of Chang in the above manner for the purpose of improving the short channel effect [0005].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Koike et al (US20100155951A1) A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/15/26
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