Prosecution Insights
Last updated: July 17, 2026
Application No. 18/662,801

DISPLAY DEVICE

Non-Final OA §112
Filed
May 13, 2024
Priority
Sep 12, 2023 — RE 10-2023-0121084
Examiner
YI, CHANGHYUN
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1009 granted / 1075 resolved
+33.9% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
73 currently pending
Career history
1127
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
61.7%
+21.7% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1075 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “Display device Including Pixel Drivers and Routing Lines Adjacent to a Light-Transmitting Area” because it encompasses both the routing/layout aspect (Claim 1) and the pixel-driver architecture aspect (Claim 14) without implying features that may later be amended out. Specification The specification contains an apparent typographical error. In paragraph [0022], the phrase: "Each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eight transistor may include ..." lacks proper antecedent consistency with the previously introduced element: "an eighth transistor electrically connected between one of the plurality of bias voltage lines and the first node." It appears that "eight transistor" should read "eighth transistor." Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 10-13 and 16-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 10. Claim 10 recites: "the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eight transistor comprises..." However, the claim previously recites an "eighth transistor" and does not introduce an "eight transistor." Therefore, it is unclear whether the recited "eight transistor" refers to the previously-recited eighth transistor or to a different transistor. Accordingly, the scope of the claim cannot be determined with reasonable certainty. Applicant may overcome this rejection by amending "eight transistor" to "eighth transistor." Regarding claims 11-13, because of their dependency on claim 10, these claims are also objected for the reasons set forth above with respect to claim 10. Regarding claim 16. Claim 16 recites: "an eighth transistor electrically connected between a bias voltage line and the first node" and further recites: "the one first-direction line is the bias voltage line." The claim introduces "a bias voltage line" as though it is a newly-recited structure and subsequently equates the bias voltage line with the previously-recited "one first-direction line." As drafted, it is unclear whether the bias voltage line is intended to be identical to the previously-recited one first-direction line or whether the bias voltage line is a separate structure. Therefore, the metes and bounds of the claim are unclear. Applicant may overcome this rejection by clarifying the relationship between the one first-direction line and the bias voltage line. Regarding claims 17-20, because of their dependency on claim 16, these claims are also objected for the reasons set forth above with respect to claim 16. Regarding claim 20. Claim 14 recites: "a gate initialization voltage line" Claim 20 recites: "one gate initialization voltage line adjacent to a boundary between the first light emitting pixel driver and the fifth light emitting pixel driver." It is unclear whether the recited "one gate initialization voltage line" refers to the previously-recited gate initialization voltage line or to a newly-recited gate initialization voltage line. Because the relationship between these structures is not clearly defined, the scope of the claim cannot be determined with reasonable certainty. Applicant may overcome this rejection by clarifying whether the recited gate initialization voltage line is the same as, or different from, the previously-recited gate initialization voltage line. Allowable Subject Matter Claims 1-9 and 11-15 are allowed. Furthermore, the claims 10-13 and 16-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1. Jeon (US 11665937) teaches a display panel including a display area and a transmission area (TA), wherein the display area at least partially surrounds the transmission area. See, e.g., FIGS. 1A, 2A, 2B, 3, and 4 and the corresponding description of the transmission area (TA) and display area (DA). Jeon further teaches routing display lines around the transmission area. In particular, Jeon discloses that scan lines (SL), data lines (DL), and electrode voltage lines (HL) are arranged to bypass along edges of the transmission area (TA). Jeon additionally teaches first-direction scan lines and electrode voltage lines extending in a first direction and including bypass portions that detour the transmission area. See FIG. 4 and the accompanying description of line routing around the transmission area. Zhang (US 11302759) teaches an OLED display device including a display area having a non-transparent display area (10a) and a transparent display area (10b). Zhang further teaches first OLED pixels arranged in an array within the non-transparent display area and second OLED pixels disposed within the transparent display area. Zhang expressly teaches that the transparent display area provides a light-transmitting function when the second OLED pixels are not driven. See, e.g., FIGS. 1, 2, 7, 10, 12, and 15 and the corresponding description of transparent display area 10b and second OLED pixels 13. Accordingly, the prior art of record teaches: • a display area including a light-transmitting or transparent area; • OLED pixel drivers arranged in a display panel; • first-direction signal lines; • bypass routing of signal lines around a transmission area; and • transparent display regions having light-transmitting functionality. However, the prior art of record, including Jeon and Zhang, either alone or in combination, fails to teach or suggest the claimed arrangement in which a light-transmitting area comprises a contact point at which four light-emitting pixel drivers contact each other and a first-direction line includes a bypass portion configured to bypass that light-transmitting area. More specifically, Jeon's transmission area is a dedicated transmission opening around which display lines are routed. Although Jeon teaches bypass portions formed in scan lines, data lines, and electrode voltage lines, Jeon does not disclose locating the transmission area at a contact point shared by four adjacent light-emitting pixel drivers. Likewise, Zhang teaches transparent display areas and OLED pixel arrangements within those transparent display areas, but Zhang does not disclose or suggest a light-transmitting area positioned at a common contact point of four adjacent light-emitting pixel drivers. Nor does Zhang disclose routing a first-direction line around such a four-pixel-driver contact-point light-transmitting area. However, neither reference discloses or suggests a geometric relationship in which four adjacent light-emitting pixel drivers meet at a common contact point that defines the location of a light-transmitting area. Further, neither reference discloses or suggests configuring a bypass portion of a first-direction line relative to such a four-pixel-driver contact-point structure. Accordingly, the recited arrangement of a light-transmitting area located at a contact point shared by four adjacent light-emitting pixel drivers, together with the associated bypass routing of the first-direction line around that light-transmitting area, is considered to distinguish the claimed invention from the prior art of record. Regarding claim 14. Zhang (US 11990096) teaches OLED pixel circuits employing multi-transistor pixel-driver architectures. In particular, Zhang discloses a 7T1C pixel circuit in FIG. 1 and further teaches that the disclosed pixel circuit may alternatively be implemented as an 8T1C pixel circuit. Specifically, Zhang discloses, with reference to FIG. 13 and the corresponding description, an 8T1C pixel circuit including eight transistors (M1-M8) and one storage capacitor (Cst). Zhang further teaches pixel-driving architectures employing both LTPS and IGZO transistors. For example, Zhang teaches that transistors M4 and M5 may be IGZO transistors while the remaining transistors may be LTPS transistors. Lee (US 11177288) teaches a display device including thin-film transistors formed from different semiconductor layers. Lee teaches embodiments in which a first semiconductor layer and a second semiconductor layer are disposed in different layers of the display structure and further teaches that the first semiconductor layer may comprise a polysilicon semiconductor layer while the second semiconductor layer may comprise an oxide semiconductor layer. Lee therefore teaches the use of different semiconductor layers and corresponding transistor structures within a display pixel-driver architecture. Accordingly, the prior art of record teaches the general pixel-driver architecture recited in claim 14, including multi-transistor OLED pixel circuits, 8T pixel-driver configurations, transistors formed from different semiconductor layers, polysilicon and oxide-semiconductor transistor structures, and light-emitting pixel drivers arranged in a display panel. However, the prior art of record fails to teach or suggest a plurality of adjacent light-emitting pixel drivers wherein the channel portion of a first transistor of a first light-emitting pixel driver is congruent with the channel portion of a corresponding first transistor of an adjacent second light-emitting pixel driver, as recited in claim 14. More specifically, Zhang is directed to pixel-circuit operation, scan driving, compensation techniques, reset operations, and transistor implementations within OLED pixel circuits, while Lee is directed to semiconductor-layer arrangements and TFT structures. Neither reference discloses or suggests any geometric relationship between corresponding transistor channel portions belonging to different pixel drivers. Further, the references do not disclose or suggest configuring adjacent pixel drivers such that corresponding first-transistor channel portions are congruent with one another. Accordingly, the recited congruent channel-portion relationship between corresponding first transistors of adjacent light-emitting pixel drivers is considered to distinguish the claimed invention from the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 13, 2024
Application Filed
Jun 08, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.2%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1075 resolved cases by this examiner. Grant probability derived from career allowance rate.

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