DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/14/2024 and 09/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI et al. (US 20180358430 A1, see IDS dated 09/22/2025), hereinafter “Kobayashi,” in view of TAKAHASHI (US 20220247387 A1), hereinafter “Takahashi.”
Re: Independent Claim 1, Kobayashi significantly discloses a semiconductor device (See Figs. 1-4 and 6; ¶0056: silicon carbide semiconductor device is a MOSFET) comprising:
a semiconductor substrate (Fig. 1: silicon carbide base 100, n+-type silicon carbide substrate 1; see ¶0071);
trenches provided from an upper surface of the semiconductor substrate (Fig. 1: trench 18), each extending in a first direction in the upper surface (Fig. 1: trench 18 extending in a perpendicular direction, i.e., first direction, to the width direction (e.g., A-A’ reference line); Fig. 6: trench 18 extending in first direction), and arranged at intervals in a second direction intersecting the first direction in the upper surface (Fig. 1: trenches 18 arranged at intervals in the width direction A-A’ in Fig. 1, i.e., second direction);
a gate insulating film covering an inner surface of each of the trenches (Fig. 1: gate insulating film 9); and
a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film (Fig. 1: gate electrode 10 insulated by film 9),
wherein the semiconductor substrate includes:
a source region of n-type exposed on the upper surface of the semiconductor substrate and being in contact with the gate insulating film in each of the trenches (Fig. 1: n+-type source region 7 in contact with gate insulating film 9; see ¶0069 and Fig. 3);
a body region of p-type being in contact with the gate insulating film in each of the trenches at a position below the source region (Fig. 1: p-type base layer 6, i.e., p-type body region, in contact with gate insulating film 9 and below source 7; see ¶0069 and Fig. 3);
a drift region of n-type being in contact with the gate insulating film in each of the trenches at a position below the body region and separated from the source region by the body region (Fig. 1: n−-type drift layer 2 and lower n-type region 5, which are in contact, comprise a drift region of n-type, e.g., n-type drift region 2/5; n-type drift region 2/5 is in contact with gate insulating film 9 at position below p-type body region 6; see ¶0072 and Fig. 3);
bottom regions of p-type each extending in the first direction so as to be in contact with the gate insulating film at a bottom surface of corresponding one of the trenches and being in contact with the drift region (Fig. 1: p+-type region 3, i.e., bottom regions of p-type, extend in a perpendicular direction, i.e., first direction, w.r.t. the width direction A-A’, and in contact with drift region 2/5; ¶0059: the first p+-type region 3 may be formed by self-alignment, i.e., formed using a mask that is used when forming the trench 18. In this manner, the first p+-type region 3 is formed using the same mask and therefore, the first p+-type region 3 and the trench 18 are formed without deviation in the formation position (alignment). In other words, the bottom regions of p-type extend along the first direction corresponding to the trenches.; ¶0077: p+-type region 3 is selectively formed at the bottom of the trench 18);
electric field relaxation regions of p-type disposed below the body region (See Figs. 2, 4, 6 and combined view of Figs. 1-4 and 6 provided below; Fig. 2: lower second p+-type region 4a, and an upper second p+-type region 4b are selectively provided and disposed below body region 6, i.e., regions 4a/b are electric field relaxation regions), connected to the body region (See Figs. 2 and 4; Fig. 2: regions 4a/b are connected to body region 6), extending in the second direction (Fig. 2: regions 4a/b extend in the width direction B-B’, i.e., second direction), being in contact with the bottom regions (Fig. 2: 4a in contact with bottom regions 3), and arranged at intervals in the first direction (See Figs. 2, 4, 6 and combined view of Figs. 1-4 and 6 provided below; Fig. 6 shows regions 4b arranged at intervals in the first direction parallel to trenches 18; Also see Figs. 8A-8D for alternate variations of regions 4b); and
contact regions of p-type each exposed on the upper surface of the semiconductor substrate and being in contact with the body region (See Figs. 3, 4 and 7; Fig. 4: p+-type contact region 8 exposed on upper surface b-b’ and in contact with body region 6; Fig. 7 shows p-type contacts 8),
semiconductor regions located between the trenches are inter-trench semiconductor regions (See Figs. 1-4; Fig. 4: shows inter-trench regions between trenches 18; Fig. 6 shows inter-trench regions between trenches 18),
there are overlapping ranges in which each of the inter-trench semiconductor regions and each of the electric field relaxation regions overlap each other when the semiconductor substrate is viewed in plane from above (See combined view below; Fig. 6 shows regions between trenches 18 which overlap with regions 4a/b when viewed from above),
the overlapping ranges include contact overlapping ranges in which the contact regions are disposed (See Figs. 6 and 7; Fig. 6: overlapping ranges with respect to regions 4b; Fig. 7: contact regions 8) and …
…
the contact overlapping ranges and the … overlapping ranges are alternately arranged in the first direction (See Figs. 6, 7 and 8A-8D; Fig. 6 shows overlapping ranges 4b between trenches 18 while Fig. 7 shows contact regions 8. As can be seen from Figs. 6 and 7, there are contact regions and non-contact overlapping ranges in which the contact regions are not disposed with respect to regions 4b; Figs. 8A-8D show variations in structural configurations; See ¶¶0064-0065; ¶0064: Arrangement of the region S1 and the region S2 is not limited to a diagonal arrangement of the region S2 as depicted in FIG. 6. FIGS. 8A, 8B, 8C, and 8D).
However, Kobayashi does not specifically disclose
… non-contact overlapping ranges in which the contact regions are not disposed, and
… non-contact ...
In a similar field of endeavor, Takahashi discloses … non-contact overlapping ranges in which the contact regions are not disposed (Fig. 12A shows staggered P+ type contacts between adjacent trenches; ¶0290: Each of the second contact regions 113 may be formed such as to be shifted from each of the first contact regions 93 in the second direction Y such as not to face some of or all of the first contact regions 93 along the first direction X. That is, the plurality of first contact regions 93 and the plurality of second contact regions 113 may be arrayed in a staggered manner in plan view.), and
… non-contact ... (Fig. 12A shows staggered P+ type contacts between adjacent trenches. In other words, there are regions between the trenches wherein a trench having a p+ type contact does not have a p+ type contact in the adjacent trench when viewed in the plan view; ¶0290: the plurality of first contact regions 93 and the plurality of second contact regions 113 may be arrayed in a staggered manner in plan view.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. Kobayashi teaches selective placement of upper p-type regions to balance electric-field relaxation against the need for sufficient current paths (Kobayashi, ¶0062). Takahashi expressly teaches that the p+ contact regions associated with adjacent trench structures may be arrayed in a staggered manner in plan view (Takahashi, ¶0290). A person of ordinary skill seeking to optimize the spatial distribution of the p-type contacts, so that hole-extraction points (or body-contact points) are more evenly dispersed while still preserving source area, would have found in Takahashi a direct structural suggestion for achieving that distribution. Takahashi further shows that the relative density of source regions versus contact regions can be adjusted to balance on-resistance against thermal/active-clamp performance (Takahashi, ¶¶0386-0395)
Kobayashi views of Figs. 1-4 and 6 (T1 - regions of the lower second p+-type region 4a)
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Re: Claim 2, the combination of Kobayashi in view of Takahashi significantly discloses the semiconductor device according to claim 1, and wherein the contact overlapping ranges and the …overlapping ranges are alternately arranged in the second direction (See Figs. 6, 7 and 8A-8D; ¶0064: Arrangement of the region S1 and the region S2 is not limited to a diagonal arrangement of the region S2 as depicted in FIG. 6. FIGS. 8A, 8B, 8C, and 8D).
However, Kobayashi does not specifically disclose … non-contact …
Takahashi further discloses … non-contact … (Fig. 12A shows staggered P+ type contacts between adjacent trenches. In other words, there are regions between the trenches wherein a trench having a p+ type contact does not have a p+ type contact in the adjacent trench when viewed in the plan view; ¶0290: the plurality of first contact regions 93 and the plurality of second contact regions 113 may be arrayed in a staggered manner in plan view.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. A person of ordinary skill seeking to optimize the spatial distribution of the p-type contacts, so that hole-extraction points (or body-contact points) are more evenly dispersed while still preserving source area, would have found in Takahashi a direct structural suggestion for achieving that distribution. Takahashi further shows that the relative density of source regions versus contact regions can be adjusted to balance on-resistance against thermal/active-clamp performance (Takahashi, ¶¶0386-0395)
Re: Claim 4, the combination of Kobayashi in view of Takahashi significantly discloses the semiconductor device according to claim 1.
Kobayashi further discloses wherein the electric field relaxation regions are first electric field relaxation regions (Fig. 6: T1 regions of the lower second p+-type region 4a), the overlapping ranges are first overlapping ranges (Fig. 6: T1 overlaps ranges between trenches 18), the contact overlapping ranges are first contact overlapping ranges (Fig. 7 shows contact regions 8 which overlap with T1 regions shown in Fig. 6), the … overlapping ranges are first … overlapping ranges (Fig. 6: T1 overlaps ranges between trenches 18),
the semiconductor substrate further includes second electric field relaxation regions of p-type (Fig. 6 shows relaxation regions 4b), each of the second electric field relaxation regions is disposed below the body region (Fig. 2 shows regions 4b below body region 6), is connected to the body region (Fig. 2 shows 4b connected to body region 6), extends in a third direction intersecting the first direction and the second direction (Fig 6 shows 4b may be structured along a diagonal direction, in plan view, with respect to the first and second directions. Figs. 8C and 8D show additional structural variations), and is in contact with each of the bottom regions (Fig. 2 shows 4a/b in contact with bottom regions 3),
the second electric field relaxation regions are arranged at intervals in a direction intersecting the third direction (Fig. 6: regions 4b are arranged at intervals which intersect the third diagonal direction; also see Figs. 8C and 8D), there are second overlapping ranges in which each of the inter-trench semiconductor regions and each of the second electric field relaxation regions overlap each other when the semiconductor substrate is viewed in plane from above (See Figs. 6, 8C and 8D; See ¶¶0064-0065; ¶0064: Arrangement of the region S1 and the region S2 is not limited to a diagonal arrangement of the region S2 as depicted in FIG. 6. FIGS. 8A, 8B, 8C, and 8D),
the second overlapping ranges include second contact overlapping ranges in which the contact regions are disposed (See Figs. 6 and 7 for contact overlapping ranges) and second … overlapping ranges in which the contact regions are not disposed (See Figs. 6, 8C and 8D), and the second contact overlapping ranges and the second … overlapping ranges are alternately arranged in the first direction (See Figs. 6, 8C and 8D; See ¶¶0064-0065).
However, Kobayashi does not specifically disclose … non-contact …
Takahashi further discloses … non-contact … (Fig. 12A shows staggered P+ type contacts between adjacent trenches. In other words, there are regions between the trenches wherein a trench having a p+ type contact does not have a p+ type contact in the adjacent trench when viewed in the plan view; ¶0290: the plurality of first contact regions 93 and the plurality of second contact regions 113 may be arrayed in a staggered manner in plan view.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. A person of ordinary skill seeking to optimize the spatial distribution of the p-type contacts, so that hole-extraction points (or body-contact points) are more evenly dispersed while still preserving source area, would have found in Takahashi a direct structural suggestion for achieving that distribution. Takahashi further shows that the relative density of source regions versus contact regions can be adjusted to balance on-resistance against thermal/active-clamp performance (Takahashi, ¶¶0386-0395)
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over KOBAYASHI et al. (US 20180358430 A1) in view of TAKAHASHI (US 20220247387 A1) and NINOMIYA (US 20050247957 A1), hereinafter “Ninomiya.”
Re: Claim 5, the combination of Kobayashi in view of Takahashi significantly discloses the semiconductor device according to claim 1.
Kobayashi also discloses further comprising:
an interlayer insulating film covering an upper surface of the gate electrode (Fig. 1: interlayer insulating film 11 covering gate electrodes 10; ¶0079: interlayer insulating film 11 is formed on the entire front surface of the silicon carbide base 100 so as to cover the gate electrodes 10) and having a contact hole above the upper surface of the semiconductor substrate (Fig. 1: opening between IL film 11, i.e., contact hole, allows contact with source electrode 12); and
an upper electrode covering a range extending over an upper surface of the interlayer insulating film and an inner surface of the contact hole (Fig. 1: source electrode 12), being in contact with the upper surface of the semiconductor substrate in the contact hole (Fig. 1: source electrode 12 in contact with upper surface through IL film 11 opening), and being insulated from the gate electrode by the interlayer insulating film (¶0070: The source electrode (first electrode) 12 is in contact … via contact holes opened in the interlayer insulating film 11 and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11),
However, the combination of Kobayashi in view of Takahashi does not disclose wherein the upper electrode includes: a tungsten-containing layer disposed in the contact hole; and an aluminum-containing layer covering the upper surface of the interlayer insulating film and an upper surface of the tungsten-containing layer.
In a similar field of endeavor, Ninomiya discloses wherein the upper electrode includes:
a tungsten-containing layer disposed in the contact hole (Fig. 2B: tungsten plug 112; ¶0030: contact hole is filled with a tungsten plug 112); and
an aluminum-containing layer covering the upper surface of the interlayer insulating film and an upper surface of the tungsten-containing layer (¶0042: This aluminum film is electrically connected to the tungsten, and the tungsten plug buried in the semiconductor substrate operates as a portion of the source electrode.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current invention, would have been motivated to use tungsten as a plug metal due to its ability to fill contact holes having a small aperture (See Ninomiya, ¶0041) and then applying aluminum in order to complete the electrical connection (See Ninomiya, ¶0031).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The current prior art of record, alone or in combination, does not teach the specific features disclosed in claim 3.
Kobayashi has selective p-type connections regions (S1/S2) and an n-type region in some areas between the body and lower p-type structures. However, it does not teach an upper n-type drift region that sits between each of the electric field relaxation regions and the body region, while contacting the gate insulating film below the body. Kobayashi discloses that where the upper p+ type region 4b is present, there is a continuous p-type path instead of the required n-type layer as required by claim 3.
Takahashi discloses a trench MOSFET stack having a source, body, and drift region. However, it does not disclose the p-type electric field relaxation regions of Claim 1 which extend in the second direction contacting the bottom regions and arranged at intervals. Without those regions, it cannot teach the upper n-type drift region of Claim 3 that must be placed between said regions and the body.
Therefore, neither reference, alone or in combination, disclose the n-type upper drift region which is required between every electric field relaxation region and the body while remaining in contact with the gate insulating film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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