DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 6/18/26.
Applicant’s election without traverse of Species B (Fig. 2) in the reply filed on 8/ is acknowledged. Claims 8-9 are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/14/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-7 and 10-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 1 and 11 recite in part the limitations:
“a backside back-end-of-the-line (BEOL) structure located on a backside of the FEOL level and comprising a plurality of first wires having a first cross sectional area and a first thermal resistance,
a frontside BEOL structure located on a frontside of the FEOL level and comprising a plurality of second wires having a second cross sectional area and a second thermal resistance,
wherein the second cross sectional area is less than the first cross sectional area and the second thermal resistance is greater than the first thermal resistance”
The metes and bounds of the claimed limitation can not be determined for the following reasons:
Paragraph 14 makes it clear that the cross sectional area and the thermal resistance are properties of wires, and not of the whole BEOL structures.
However, the claims require a plurality of first wires to have a single “first cross sectional area” and to have a single “first thermal resistance”, and the claims require a plurality of second wires to have a single “second cross sectional area” and to have a single “second thermal resistance”. Because of this mismatch between plurality and single properties, it is unclear if the claim requires that any single wire can have the first cross sectional area and the first thermal resistance, or if it requires each of the plurality of first wires to each have the first cross sectional area and the first thermal resistance, or if the totality of all of the wires in the plurality of first wires must sum to the first cross sectional area and sum to the first thermal resistance.
The unclarity described in the previous paragraph also pertains to the plurality of second wires, with the second wires being analogous to the first wires, with the second cross sectional area being analogous to the first cross sectional area, and with the second thermal resistance being analogous to the first thermal resistance.
Claims 2-7 and 10 depend from claim 1. Claims 12-19 depend from claim 11. The dependent claims inherit the deficiencies of the claim(s) from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6, 10-12, 16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0266289 a1 (“Jin”) in view of US 2023/0207471 A1 (“Mallik”).
Jin teaches, for example:
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Jin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. An electronic structure comprising: a semiconductor die (see e.g. Fig. 8) comprising
a front-end-of-the-line (FEOL) level (comprising e.g. isolation structure 202 and the wirings and devices therein) comprising at least one semiconductor device (see e.g. transistors, capacitors, or inductors, see e.g. para 43),
a backside back-end-of-the-line (BEOL) structure (comprising e.g. second dielectric structure 221 and/or third dielectric structure 222, and wirings therein) located on a backside of the FEOL level and comprising a plurality of first wires (e.g. 211, 212) having a first cross sectional area and a first thermal resistance,
a frontside BEOL structure (comprising e.g. first dielectric structure 220 and wirings therein) located on a frontside (top, as shown in Fig. 8) of the FEOL level and comprising a plurality of second wires (e.g. 206, 207) having a second cross sectional area and a second thermal resistance,
wherein the second cross sectional area is less than the first cross sectional area and the second thermal resistance is greater than the first thermal resistance, and
a through via structure (comprising e.g. second connecting structure 213 and possibly 208 and/or 209) extending entirely through the semiconductor die (213, 209, 209, and the top unlabeled pad in Fig. 8 extend through all of 220, 202, 200, 221, and 222, and hence extend entirely through the semiconductor die).
Jin does not explicitly teach: a thermal dissipating structure located above the backside BEOL structure; and a packaging substrate located beneath the frontside BEOL structure and electrically connected to the through via structure.
Mallik teaches, for example:
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Mallik teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Jin, a thermal dissipating structure (e.g. “heat spreaders and/or heat sinks 750”) located above the backside BEOL structure (it is on the backside of the chip 301); and a packaging substrate (comprising e.g. “host component 705” which may be a package substrate, see Fig. 8 and e.g. para 51-52) located beneath the frontside BEOL structure (it is on the front side of the die 301) and electrically connected to the through via structure (705 electrically connects to the vias 235 via “interconnect interfaces 240” and “FLI features” that are solder microbumps, see e.g. para 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Mallik to the invention of Jin. The motivation to do so is that the combination produces the predictable results of connecting the semiconductor die to a backside heat spreader and/or heat sink, which may be advantageous wherein the semiconductor die has multiple CPU cores (see e.g. para 52), which one of ordinary skill in the art would recognize as producing much heat that needs to be dissipated away from the die; furthermore, it would allow the die to be attached to a host component such as a package substrate that can connect to other computer devices by connecting to another host such as a printed circuit board or a mother board (see e.g. para 52).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Jin and Mallik together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The electronic structure of Claim 1, wherein the thermal dissipating structure comprises a thermal interface material, a lid, a heat sink (see Mallik’s 750; the discussion of obviousness and motivation was explained with claim 1) or any combination thereof.
6. The electronic structure of Claim 1, wherein the FEOL level further comprises a semiconductor device layer (comprising e.g. Jin’s 200, which can be a semiconductor substrate) located beneath the at least one semiconductor device.
10. The electronic structure of Claim 1, wherein the frontside BEOL structure is attached to the packaging substrate by a plurality of solder balls, wherein at least one of the solder balls of the plurality of solder balls is in contact with the through via structure (see Mallik’s solder balls 610 that connect to vias 235 via pillars 240).
Jin teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
11. An electronic structure comprising: a semiconductor die (see e.g. Fig. 8) comprising
a front-end-of-the-line (FEOL) level (comprising e.g. isolation structure 202 and the wirings and devices therein) comprising at least one semiconductor device (see e.g. transistors, capacitors, or inductors, see e.g. para 43),
a backside back-end-of-the-line (BEOL) structure (comprising e.g. second dielectric structure 221 and/or third dielectric structure 222, and wirings therein) located on a backside of the FEOL level and comprising a plurality of first wires (e.g. 211, 212) having a first cross sectional area and a first thermal resistance,
a frontside BEOL structure (comprising e.g. first dielectric structure 220 and wirings therein) located on a frontside (top, as shown in Fig. 8) of the FEOL level and comprising a plurality of second wires (e.g. 206, 207) having a second cross sectional area and a second thermal resistance,
wherein the second cross sectional area is less than the first cross sectional area and the second thermal resistance is greater than the first thermal resistance, and
a through via structure (comprising e.g. second connecting structure 213 and possibly 208 and/or 209) extending entirely through the semiconductor die (213, 209, 209, and the top unlabeled pad in Fig. 8 extend through all of 220, 202, 200, 221, and 222, and hence extend entirely through the semiconductor die).
Jin does not explicitly teach: a carrier wafer located above the backside BEOL structure; a thermal dissipating structure located above the backside BEOL structure; and a packaging substrate located beneath the frontside BEOL structure and electrically connected to the through via structure.
Mallik teaches, for example:
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Mallik teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Jin, a carrier wafer (e.g. one or the other of heat spreaders and/or heat sinks 750, see e.g. para 52, one of which may be considered a “carrier wafer”) located above the backside BEOL structure; a thermal dissipating structure (e.g. the other of “heat spreaders and/or heat sinks 750” not being the carrier wafer) located above the backside BEOL structure (it is on the backside of the chip 301); and a packaging substrate (comprising e.g. “host component 705” which may be a package substrate, see Fig. 8 and e.g. para 51-52) located beneath the frontside BEOL structure (it is on the front side of the die 301) and electrically connected to the through via structure (705 electrically connects to the vias 235 via “interconnect interfaces 240” and “FLI features” that are solder microbumps, see e.g. para 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Mallik to the invention of Jin. The motivation to do so is that the combination produces the predictable results of connecting the semiconductor die to a backside heat spreader and/or heat sink, which may be advantageous wherein the semiconductor die has multiple CPU cores (see e.g. para 52), which one of ordinary skill in the art would recognize as producing much heat that needs to be dissipated away from the die; furthermore, it would allow the die to be attached to a host component such as a package substrate that can connect to other computer devices by connecting to another host such as a printed circuit board or a mother board (see e.g. para 52).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Jin and Mallik together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
12. The electronic structure of Claim 11, wherein the thermal dissipating structure comprises a thermal interface material, a lid, a heat sink (see Mallik’s 750; the discussion of obviousness and motivation was explained with claim 1) or any combination thereof.
16. The electronic structure of Claim 11, wherein the FEOL level further comprises a semiconductor device layer (comprising e.g. Jin’s 200, which can be a semiconductor substrate) located beneath the at least one semiconductor device.
18. The electronic structure of Claim 11, further comprising
an upper backside BEOL structure via structure (see e.g. 214) contacting one of the first wires of the plurality of first wires,
wherein the upper backside BEOL structure via structure is electrically connected to the through via structure (through 215), and
wherein the first wiring that contacts the upper backside BEOL structure via structure is in direct physical contact with the at least one semiconductor device (see e.g. Fig. 8).
19. The electronic structure of Claim 11, wherein the frontside BEOL structure is attached to the packaging substrate by a plurality of solder balls, wherein at least one of the solder balls of the plurality of solder balls is in contact with the through via structure (see Mallik’s solder balls 610 that connect to vias 235 via pillars 240).
Claim(s) 3-5, 7, 13-15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Mallik and US 2023/0187412 A1 (“Gao”).
Jin and Mallik teach claims 1 and 11, as discussed above, but do not explicitly teach:
a redistribution layer positioned between the thermal dissipating structure and the backside BEOL structure, wherein the redistribution layer comprises a redistribution wire the contacts the through via structure and is electrically connected to the at least one semiconductor device through one of the first wires present in the backside BEOL structure (it would have been obvious to one of ordinary skill in the art to connect to vias in Jin’s chip, to connect from e.g. IC dies embedded in 705, see e.g. para 51) (claims 3 and 13);
wherein the redistribution wire is embedded in a redistribution dielectric material having a thermal conductivity in the range of 1.2-30 W/m-K or above (claims 4 and 14);
wherein the redistribution layer is spaced apart from the thermal dissipating structure by a dielectric layer (claims 5 and 15); or
wherein the plurality of first wires of the backside BEOL structure are embedded in a backside BEOL structure dielectric material having a thermal conductivity in the range of 1.2-30 W/m-K or above (claims 7 and 17).
Gao teaches, for example:
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Gao teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Jin and Mallik:
a redistribution layer (see “intervening routing structure (not shown)”, para 31) positioned between the thermal dissipating structure (e.g. Gao’s 28, see Fig. 6) and the backside BEOL structure (e.g. top of top die 1c, Fig. 6), wherein the redistribution layer comprises a redistribution wire the contacts the through via structure and is electrically connected to the at least one semiconductor device through one of the first wires present in the backside BEOL structure (it would have been obvious to one of ordinary skill in the art to connect to vias in Jin’s chip, to connect from e.g. IC dies embedded in Mallik’s package substrate 705, see e.g. para 51; and/or to connect to thermal vias such as Gao’s 29) (claims 3 and 13);
wherein the redistribution wire is embedded in a redistribution dielectric material having a thermal conductivity in the range of 1.2-30 W/m-K or above (see e.g. para 58 and 68, wherein Jin envisions use of a list of many materials, including silicon nitride, which are the same type of materials Applicant envisions; see Applicant’s para 19, 27; since the material is the same, the thermal conductivity would be the same) (claims 4 and 14);
wherein the redistribution layer is spaced apart from the thermal dissipating structure by a dielectric layer (e.g. Mallik’s “heat spreaders” connected to the heat sinks, such heat spreaders well-known in the art to be dielectric layers) (claims 5 and 15); and
wherein the plurality of first wires of the backside BEOL structure are embedded in a backside BEOL structure dielectric material having a thermal conductivity in the range of 1.2-30 W/m-K or above (see e.g. para 58 and 68, wherein Jin envisions use of a list of many materials, including silicon nitride, which are the same type of materials Applicant envisions; see Applicant’s para 19, 27; since the material is the same, the thermal conductivity would be the same) (claims 7 and 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Gao to the invention of Jin and Mallik. The motivation to do so is that the combination produces the predictable results of attaching a heat sink to the device, either directly or indirectly, allowing for power, ground, and other traces as well as providing heat paths from the stacked dies (see e.g. Gao, para 31), to thus provide adequate heat dissipation for devices such as vertically integrated stacks such as high bandwidth memory (see e.g. Gao, para 3, 11).
Applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2023/0187273 A1 (“Murthy”) teaches large vias and interconnections for power on the backside 117 and smaller vias and interconnects on the front side 115 (see e.g. cover figure).
US 2022/0415904 A1 (“Sharma”) teaches stacks of BEOLS on front and backs of devices, having a through via structure 730 therein, see e.g. cover figure.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
