Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/14/2024 was filed prior to the mailing date of this action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In paragraph 00104, line 1, “one or more cooling channels 182” is recited although it is later referred to as “cooling system 182” in line 2 of the same paragraph.
In paragraph 00104, line 9, and paragraph 00134, line 3, “cooling system 184” is recited although “cooling system” was previously associated with 182 (e.g. “cooling system 182” in paragraph 00104, line 2).
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“a cooling system to cool the head” in claim 15
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 20, “different vertical positions along of the retaining ring” is recited in lines 4-5, which is rejected under 112(b) for indefiniteness under vagueness, as “along of” is being used in defining the locations of the different vertical positions relative to the retaining ring. For the purposes of examination, as best understood by the examiner, the language will be interpreted as “different vertical positions along the retaining ring.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nabeya et al. (US 20220048157 A1).
Regarding claim 1, Nabeya teaches (reproduced and annotated Figs. below) a surface processing system for a semiconductor workpiece, comprising: a platen (polishing table 18 as shown in annotated Fig. 1 below) configured to rotate about an axis (“The polishing table 18 is coupled via a table shaft 18a to a table motor 29 disposed below the polishing table 18, so that the polishing table 18 is rotatable about the table shaft 18a.,” [0051], Nabeya); a surface processing pad (polishing pad 19 as shown in annotated Fig. 1 below) on the platen (“a polishing table 18 for supporting a polishing pad 19,” [0050], Nabeya); a workpiece carrier (substrate holding apparatus 1 as shown in annotated Figs. 1 and 2) operable to bring a semiconductor workpiece into contact with the surface processing pad (“a substrate holding apparatus 1 for holding a wafer W as an example of a substrate, which is an object to be polished, and pressing the wafer W against the polishing pad 19 on the polishing table 18,” [0050], Nabeya), the workpiece carrier comprising a head (head body 2 as shown in annotated Fig. 2 below) and a retaining ring (retaining ring 3 as shown in annotated Figs. 1 and 2 below) around at least a portion of the head (“The retaining ring 3 is disposed so as to surround the carrier 43 of the head body 2 and the elastic membrane 10 [elastic membrane 10 is attached to the lower surface of the head body 2],” [0062], Nabeya), wherein at least one of the head and the retaining ring is movable relative to each other (“the retaining ring 3 can move smoothly in the vertical direction relative to the head body 2,” [0068], Nabeya).
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Regarding claim 2, Nabeya teaches the claimed invention as rejected above in claim 1, wherein the retaining ring is movable in a direction generally perpendicular to a surface of the surface processing pad independently of the head (“The retaining ring 3 is configured to be vertically movable independently of the head body 2,” [0058], Nabeya).
Regarding claim 3, Nabeya teaches the claimed invention as rejected above in claim 1, wherein the surface processing pad comprises a polishing pad (polishing pad 19 as shown in annotated Fig. 1 above).
Regarding claim 9, Nabeya teaches the claimed invention as rejected above in claim 1, wherein the workpiece carrier is operable to provide a first downforce from the head on the surface processing pad (“Thus, in the polishing head 1, pressing forces applied to the wafer W can be adjusted at respective zones of the wafer W by adjusting pressures of the fluid supplied to the respective pressure chambers 16a to 16f formed between the head body 2 and the elastic membrane 10,” [0060], Nabeya) that is a different magnitude relative to a second downforce from the retaining ring on the surface processing pad (“When the pressure regulator 65 supplies a fluid (e.g., air) into the retaining ring pressure chamber 63, the rolling diaphragm 62 pushes down the piston 61, which in turn pushes down the retaining ring 3 in its entirety. In this manner, the retaining ring pressing mechanism 60 presses the lower surface of the retaining ring 3 against the polishing surface 19a of the polishing pad 19,” [0064], Nabeya).
Regarding claim 10, Nabeya teaches the claimed invention as rejected above in claim 1, , comprising one or more cavities in the head (pressure chambers 16a to 16f as shown in annotated Fig. 2 above), the one or more cavities configured to modify a pressure between the semiconductor workpiece and the surface processing pad (“in the polishing head 1, pressing forces applied to the wafer W can be adjusted at respective zones of the wafer W by adjusting pressures of the fluid supplied to the respective pressure chambers 16a to 16f formed between the head body 2 and the elastic membrane 10”; “the elastic membrane comprises: a contact portion to be brought into contact with the substrate for pressing the substrate against the polishing pad,” [0060] & [0025], Nabeya).
Regarding claim 11, Nabeya teaches the claimed invention as rejected above in claim 1, wherein the one or more cavities define a plurality of zones (“A plurality of pressure chambers (i.e., a circular central pressure chamber 116a located at a center of the elastic membrane, annular edge pressure chambers 116g, 116h located at the outermost part of the elastic membrane, and annular intermediate pressure chambers 116b, 116c, 116d, 116e, and 116f located between the central pressure chamber 116a and the edge pressure chambers 116g, 116h) are formed by the circumferential walls 110a to 110h,” [0006], Nabeya; as shown in annotated Fig. 22 below).
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Regarding claim 12, Nabeya teaches the claimed invention as rejected above in claim 1, wherein the one or more cavities each are operable to accommodate a fluid to modify a pressure between the semiconductor workpiece and the surface processing pad (“This pressure chamber is supplied with a fluid, such as air, to press the wafer through the elastic membrane with a fluid pressure”; “Therefore, in the conventional substrate holding apparatus, an allowable value is set for the pressure difference of fluid supplied respectively to the adjacent pressure chambers,” [0005] & [0027], Nabeya).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Koike et al. (DE 10314212 A1).
Regarding claim 4, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the surface processing pad comprises a grind disk.
However, Koike does teach a method and device for polishing a semiconductor workpiece, wherein the surface processing pad comprises a grind disk (grinding wheel or belt can be used as an alternative method of mechanically modifying the profile of the substrate or workpiece compared to using a polishing wheel or belt [polishing wheel as shown in annotated Fig. 3 below], [0143], Koike).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Koike to apply higher friction and pressure onto the surface of the workpiece for mechanical modifying the workpiece’s profile compared to the polishing pad ([0142] & [0143], Koike).
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Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Miller et al. (US 5081421 A).
Regarding claim 5, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the head comprises an electrically conductive material.
However, Miller does teach a method and apparatus for manufacturing a semiconductor device, wherein the head comprises an electrically conductive material (“Both the polishing table and the wafer carrier may be of a conducting material, such as a cermet or a metal, e.g. stainless steel, aluminum,” col. 4, lines 60-63, Miller).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Miller to provide a method for detecting the capacitance between a workpiece and an electrode in the head via a measuring electrode during the semiconductor workpiece polishing process (col. 12, lines 25-36, Miller; col. 9, lines 44-49, Miller).
Regarding claim 6, Nabeya, as modified, teaches the claimed invention as rejected above in claim 5.
Nabeya, as modified, does not teach a method and apparatus for the electrically conductive material provides a conductive path from the semiconductor workpiece to a bias source.
However, Miller does teach a method and apparatus for electric-processing a substrate, wherein the electrically conductive material provides a conductive path from the semiconductor workpiece to a bias source (“In yet another embodiment, shown in FIG. 14, the thickness of a dielectric layer on only one face of the wafer (one facing the polishing pad) may be measured by an arrangement similar to that of FIG. 6 but with the electrode structure 25 built not in the polishing table 11 but in the wafer carrier 12 The components of the electrode structure 25 in this embodiment are the same as previously described, namely, a measuring electrode 26, a guard electrode 27, insulators 28 and 29 and electrical connections 31 and 32 from measuring electrode 26 and guard electrode 27, which are made to the electronics identical to electronics of FIGS. 9 and 10. In this case, as before, the plastic adhesive backing on insert pad 15 must be perforated to ensure electrically conductive path from the wafer to the electrode structure,” col. 9, lines 44-59, Miller; “the drive to the measuring electrode 26 is constantly servoed to such a value that its displacement current is constant,” col. 8, lines 55-57, Miller; as shown in annotated Figs. 6, 9, and 14 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, as modified, to provide a method for detecting the capacitance between a workpiece and an electrode in the head via a measuring electrode during the semiconductor workpiece polishing process (col. 12, lines 25-36, Miller; col. 9, lines 44-49, Miller).
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Trojan (US 20210031331 A1).
Regarding claim 7, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the head is operable to provide a vacuum for holding the semiconductor workpiece.
However, Trojan does teach a method and apparatus for workpiece polishing, wherein the head is operable to provide a vacuum for holding the semiconductor workpiece (“In some embodiments, the wafer 155 can be held, for example, by force of a vacuum. For example, the wafer carrier 150 can hold or attach wafer 155 with a vacuum system,” [0049], Trojan; as shown in annotated Fig. 2 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Trojan to allow for the surface of the workpiece that requires polishing to properly face the surface processing pad or polishing pad when the workpiece is attached to the workpiece carrier ([0049], Trojan).
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Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Chandrasekaran (US 20040038623 A1).
Regarding claim 8, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the semiconductor workpiece comprises a first side that remains in electrically conductive contact with at least a portion of the head during a surface processing operation.
However, Chandrasekaran does teach a method and system for planarizing a semiconductor workpiece, wherein the semiconductor workpiece comprises a first side that remains in electrically conductive contact with at least a portion of the head during a surface processing operation (“the first carrier sensor 440 is held against and in electrical contact with the back face of the substrate 12 [first carrier sensor 440 is a part of the carrier head],” [0077], Chandrasekaran; as shown in annotated Fig. 10 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Chandrasekaran to detect the electric potential between the workpiece carrier and platen (via a pad sensor installed onto the platen) to determine if the planarizing process has reached an endpoint necessary to stop the workpiece from rubbing against the surface processing pad ([0077], Chandrasekaran).
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Cook et al. (CN 1664992 A).
Regarding claim 13, Nabeya teaches the claimed invention as rejected above in claim 10.
Nabeya does not teach the head comprises an electrically conductive layer between the semiconductor workpiece and the one or more cavities.
However, Cook does teach a polishing pad for electrochemical mechanical polishing for a semiconductor workpiece, wherein the head comprises an electrically conductive layer (“Therefore, by electrically connecting with the polishing liquid 20, or by directly with the metal layer 18 and the conductive layer 26 to realize electrical contact between the anode (substrate) and the cathode (conductive layer 26) to establish electrical connection (circuit),” pg. 5, lines 28-31 Cook; as shown in annotated Fig. 1 below) between the semiconductor workpiece and the one or more cavities (as shown in annotated Fig. 1 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Cook to combine the conductive layer with one or more cavities to form one or more conductive grooves that can provide and maintain continuous electrical power throughout the system even if the surface processing pad or polishing pad moves relative to the electrical current source (pg. 4, lines 37-38 ; pg. 5, lines 34-37, Cook)
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Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Hisano et al. (CN 115954252 A).
Regarding claim 14, Nabeya teaches the claimed invention as rejected above in claim 10.
Nabeya does not teach wherein the head comprises a thermally conductive layer between the semiconductor workpiece and the one or more cavities.
However, Hisano does teach a workpiece carrying table, wherein the head comprises a thermally conductive layer (“a metal bonding layer [40] with high thermal conductivity,” [0057] Hisano) between the semiconductor workpiece and the one or more cavities (as shown in annotated Fig. 1 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Hisano to enable the necessary heat dissipation capabilities when processing semiconductor workpieces through high-power plasma ([0002, Hisano).
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Claims 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Donofrio (US 11901181 B2).
Regarding claim 15, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach a cooling system to cool the head. This element is interpreted under 35 U.S.C. 112(f) as a fluid-based cooling system to perform the claimed function described in the specification, and equivalents thereof.
However, Donofrio does teach a method for carrier-assisted processing of semiconductor workpieces from crystalline material, comprising a cooling system (“cooling apparatus in the form of a cooled chuck 76,” col. 29, line 28, Donofrio) to cool the head (“Contact between the rigid carrier 72 and the cooled chuck 76 causes heat to be transferred from the rigid carrier 72 to the cooled chuck 76 such that the rigid carrier 72 is cooled rapidly,” col. 29, lines 29-32, Donofrio; “In certain embodiments, the cooled chuck 76A and the coolant bath 79 may be arranged in a closeable insulating vessel (not shown), whereby the vessel may be selectively opened to permit a rigid carrier 72 with attached adhesive material 68 and crystalline material substrate 60 with subsurface laser damage 66 to be placed in contact with the cooled chuck 76A for rapid fracture of the single crystalline material substrate 60,” col. 31, lines 18-25, Donofrio; as shown in annotated Fig. 10C below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Donofrio to establish a method of fracturing the crystalline material of the workpiece by cooling the workpiece carrier to the point where the workpiece carrier has a greater coefficient of thermal expansion than the semiconductor workpiece (col. 5, lines 7-14, Donofrio).
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Regarding claim 18, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the semiconductor workpiece comprises silicon carbide.
However, Donofrio does teach a method for carrier-assisted processing of semiconductor workpieces from crystalline material, wherein the semiconductor workpiece comprises silicon carbide (“In certain embodiments, the crystalline material comprises silicon carbide material,” col. 11, lines 60-61, Donofrio; as shown in annotated Fig. 19 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Donofrio to have allowed for the semiconductor workpiece to comprise of silicon carbide due to its chemical structure enabling the fabrication of electronic power, radio frequency, and optoelectronic devices (col. 2, lines 17-22, Donofrio).
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Regarding claim 19, Nabeya teaches a method for surface processing a semiconductor workpiece using a surface processing system (as shown in annotated Fig. 1 below), the method comprising: providing a semiconductor workpiece (wafer W as shown in annotated Figs. 1 and 2 below) against a surface processing pad (polishing pad 19 as shown in annotated Fig. 1 below) with a workpiece carrier (substrate holding apparatus 1 as shown in annotated Figs. 1 and 2 below), the workpiece carrier comprising a head (head body 2 as shown in annotated Fig. 2 below) and a retaining ring (retaining ring 3 as shown in annotated Figs. 1 and 2 below) around at least a portion of the head (“The retaining ring 3 is disposed so as to surround the carrier 43 of the head body 2 and the elastic membrane 10 [elastic membrane 10 is attached to the lower surface of the head body 2],” [0062], Nabeya); imparting relative motion between the retaining ring and the head (“the retaining ring 3 can move smoothly in the vertical direction relative to the head body 2,” [0068], Nabeya); and performing a surface processing operation by imparting relative motion between the surface processing pad and the silicon carbide semiconductor workpiece (“pressing the wafer W against the polishing pad 19 on the polishing table 18,” [0050], Nabeya).
Nabeya does not teach the semiconductor workpiece comprising of silicon carbide.
However, Donofrio does teach a method for carrier-assisted processing of semiconductor workpieces from crystalline material, wherein the semiconductor workpiece is a silicon carbide semiconductor workpiece (“In certain embodiments, the crystalline material comprises silicon carbide material,” col. 11, lines 60-61, Donofrio; as shown in annotated Fig. 19 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Donofrio to have allowed for the semiconductor workpiece to comprise of silicon carbide due to its chemical structure enabling the fabrication of electronic power, radio frequency, and optoelectronic.
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Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Chen et al. (US 20050113002 A1).
Regarding claim 16, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the retaining ring comprises a thermoplastic material.
However, Chen does teach a chemical-mechanical polish (CMP) retaining ring (as shown in annotated Fig. 2A below) wherein the retaining ring comprises a thermoplastic material (“The most commonly used materials for retaining ring, normally but not limited to thermosetting or thermoplastic polymer,” [0058], Chen).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Chen to allow for the retaining ring to be heated to a highly plastic state (e.g. easily stretched or molded), preventing fracture or damage to the retaining ring when exposed to the high temperatures caused by semiconductor workpiece processing ([0058], Chen).
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Madsen (US 20220235459 A1).
Regarding claim 17, Nabeya teaches the claimed invention as rejected above in claim 1.
Nabeya does not teach the retaining ring has a wall thickness of about 1 millimeter to about 40 millimeters.
However, Madsen does teach a retaining ring for workpiece processing systems, wherein the retaining ring has a wall thickness of about 1 millimeter to about 40 millimeters (“In some examples, the carrier ring 208 has a thickness of approximately 0.167″ (e.g., 4.25 mm, +/1 0.5 mm). In other examples, the thickness of the carrier ring 208 is approximately 0.101″ (e.g., 2.57 mm, +/−0.5 mm),” [0031], Madsen).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Madsen to provide the retaining ring with a reduced inner diameter that is less than the outer diameter of the workpiece, thus the allowable diameter and thickness of the retaining ring is relative to the diameter of the workpiece (pg. 6, lines 10-13, Madsen)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nabeya, in view of Torii (US 20080146123 A1).
Regarding claim 20, Nabeya teaches a retaining ring (retaining ring 3 as shown in annotated Figs. 1, 2, and 3 below) for a workpiece carrier (substrate holding apparatus 1 as shown in annotated Figs. 1 and 2 below) in a system for polishing semiconductor workpieces (“a polishing apparatus comprising: a polishing table for supporting a polishing pad; and a substrate holding apparatus configured to press a substrate against the polishing pad,” Nabeya), comprising: a plurality of grooves (plurality of radical grooves 43a as shown in annotated Fig. 3 below)
Nabeya does not teach the plurality of grooves are at different vertical positions along of the retaining ring.
However, Torii does teach an apparatus and method for semiconductor manufacturing comprising a head, polishing pad, and retaining ring wherein the plurality of grooves are at different vertical positions along of the retaining ring (“Concentric grooves 2b are grooves for purposes of changing the area of retainer ring 1 which comes into contact with polishing pad 8 as retainer ring 1 is increasingly worn in the wafer polishing operation. In this exemplary embodiment, each groove 2b has a different depth”; “On the other hand, a plurality of machined holes 18 are grooves for the purpose of changing the contact area of retainer ring 1 to polishing pad 8 in accordance with wear on retainer ring 1 during a wafer polishing operation. For this purpose, each machined hole 18 has a different depth,” [0047] & [0075], Torii; as shown in annotated Figs. 1, 4, and 9 below).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Nabeya, to incorporate the teachings of Torii to adjust the area of contact between the retaining ring and surface processing pad or polishing pad to reduce the wear on the retaining ring during the semiconductor workpiece polishing process ([0047] & [0075], Torii).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Liu (US 20190164771 A1) teaches an equipment and method for performing chemical mechanical polishing (CMP) on semiconductor wafers similar to the claimed invention (Fig. 1A)
Kwon (KR 20230071111) teaches a substrate carrier and a substrate polishing apparatus comprising a retaining ring similar to the claimed invention (Figs. 1-3).
Molnar (US 20110294399 A1) teaches an apparatus and method for chemical mechanical polishing (CMP) semiconductor workpieces (Fig. 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISHAQ M ISHAQ whose telephone number is (571)270-0696. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Posigian can be reached at 313-446-6546. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/I.M.I./Examiner, Art Unit 3723
/DAVID S POSIGIAN/Supervisory Patent Examiner, Art Unit 3723
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