Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Under USPTO rules (37 CFR § 1.56 and MPEP § 2001), all individuals tied to a patent application have a continuous duty of candor and disclosure to share material information. Submitting a WIPO publication for foreign priority with search reports does not replace a formal Information Disclosure Statement (IDS) under 37 CFR § 1.97 and § 1.98.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. Chen teaches the pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 20200058627 A1).
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CLAIM 1. Chen teaches a method of fabricating a chip package, comprises:
providing a first support carrier C (Fig. 3A);
forming first conductive bumps 308 and an interconnection device 300 on a surface on one side of the first support carrier (Fig. 3A), wherein the interconnection device has opposing active 300a and passive sides, the passive side 300b of the interconnection device being attached to the first support carrier, the active side of the interconnection device having second conductive bumps 308 (Fig. 3B);
providing at least two chips, each chip of the at least two chips [704/804] having an active side and an opposing passive side (Fig. 3D); and
connecting the active side of each chip of the at least two chips to a respective subset of the first conductive bumps and a respective subset of the second conductive bumps (Fig. 3D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)2-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200058627 A1).
CLAIM 2. Chen teaches the method of claim 1, however may not explicitly teach utilizing the specific sequencing of wherein forming the first conductive bumps and the interconnection device on the surface on one side of the first support carrier comprises:
forming a seed layer on the surface on the one side of the first support carrier;
forming a photoresist layer with a through hole pattern on a surface on one side of the seed layer that is facing away from the first support carrier, the through hole pattern including through holes penetrating the photoresist layer; forming the first conductive bumps in respective ones of the through holes; and removing the photoresist layer; and attaching the passive side of the interconnection device to a surface on the side of the seed layer that is facing away from the first support carrier.
However, Chen et al. teaches forming see material layers, forming mask patterns with openings, performing plating processes, and removing the mask and underlying see layers to form other conductive structures (such as redistribution vias and traces) within the packaging build-up. It would have been obvious to a PHOSITA at the time of the invention was made to form the conductive pillars of Claim 1 using Chen’s disclosed seed layer deposition, pattern masking, plating, and seed-etching steps. One of ordinary skill in the art would be motivated to utilize these standard seed layer and plating techniques to form the conductive pillars in order to fabricate precise, high-aspect ratio vertical interconnects using established semiconductor processing steps disclosed within Chen et al.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
CLAIM 3. Chen teaches the method of claim 1, wherein forming the first conductive bumps and the interconnection device on the surface on one side of the first support carrier comprises:
attaching the passive side of the interconnection device to the surface on one side of the first support carrier (Figs 1B & 3B);
forming a seed layer over the interconnect device and the first support carrier, the seed layer having a first portion covering a part of the surface on the one side of the first support carrier around the interconnect device, a second portion covering an active side of the interconnection device, and a third portion between the first portion and the second portion, the third portion covering a peripheral surface of the interconnection device (Chen ¶11-15 & ¶24); and
forming the first conductive bumps and the second conductive bumps, wherein the first conductive bumps are formed on a surface of the first portion of the seed layer that is facing away from the first support carrier, and the second conductive bumps are formed on a surface of the second portion of the seed layer that is facing away from the interconnection device (Chen ¶11-15 & ¶24; Figs. 1E-D & 3C-3D ).
CLAIM 4. Chen teaches the method of claim 3, wherein forming the first conductive bumps and the second conductive bumps comprises: forming a photoresist layer over the interconnect device and the first support carrier on one side of the seed layer that is facing away from the first support carrier and the interconnect device, the photoresist layer having a through hole pattern, wherein the through hole pattern includes through holes penetrating the photoresist layer; forming the first conductive bumps and the second conductive bumps in respective ones of the through holes; and removing the photoresist layer (Chen ¶24).
CLAIM 5. Chen teaches the method of claim 3, wherein before the active side of each of the at least two chips is connected to a respective subset of the first conductive bumps and a respective subset of the second conductive bumps, the method further comprising: removing the seed layer (Chen ¶24).
CLAIM 6. Chen teaches the method of claim 1, wherein before the active side of each of the at least two chips is connected to a respective subset of the first conductive bumps 308 and a respective subset of the second conductive bumps 308, the method further comprises: providing a second support carrier 1300; and attaching the passive side of each of the at least two chips 704/804 to a surface on one side of the second support carrier 1300 (Fig. 2A).
CLAIM 7. Chen teaches the method of claim 6, wherein the active sides of the at least two chips are concurrently connected to respective subsets of the first conductive bumps and respective subsets of the second conductive bumps while the at least two chips are attached to the second support carrier (Fig. 2A).
CLAIM 8. Chen teaches the method of claim 7, further comprising: forming a molded packaging layer 400/400’ between the first support carrier and the second support carrier; wherein the molded packaging layer embeds the interconnection device, the first conductive bumps, the second conductive bumps, and the at least two chips (Chen ¶19 & Fig. 2A).
CLAIM 9. Chen teaches the method of claim 8, further comprising: removing the first support carrier to expose bottom surfaces of the first conductive bumps on one side of the molded package layer; forming third conductive bumps on respective ones of the bottom surfaces of the first conductive bumps, the third conductive bumps being respectively connected to the first conductive bumps (Figs. 3F-H) and configured to connect the at least two chips to an external device (“Configured to” does not provide any further structural distinction, as the bumps of Chen are capable of the functional requirement.)
CLAIM 10. Chen teaches the method of manufacturing of claim 8, further comprising: forming a redistribution layer on the side of the molded package layer where bottom surfaces of the first conductive bumps 308 are exposed; and forming third conductive bumps 1100] on a side of the redistribution layer facing away from the first conductive bumps, wherein the first conductive bumps are connected to the third conductive bumps through the redistribution layer (Chen Fig. 3H).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005, the examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/7/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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