DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device in the reply filed on 8/11/2026 is acknowledged.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 12-15 lacks recitation in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, claims 6 12-15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
As to claim 6 Applicant does not show wherein the adhesion promotion pattern is disposed in a corner area of the semiconductor device. Figures 2a-2d and 10b show the adhesion layer near the corner but no at the or filling the corner. The figures depict the adhesion promotion layer space away from the actual corner.
As to claim 12-15, Applicant does not depict wherein the first integrated circuit comprises a first conductive connector bonded to a second integrated circuit, the first conductive connector is disposed in a passivation layer, and the adhesion promotion pattern is disposed on and in direct contact with the passivation layer. This would require a second circuit on top on top of a first circuit applicant only depict
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4 12-15 and 21-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. While applicant has support for wherein the adhesion promotion pattern is disposed between the conductive connector and a periphery of the passivation layer in a plan view applicant does not have support for wherein the adhesion promotion pattern is disposed between the conductive connector and a periphery of the passivation layer in a laminate view thus the entire breadth of the claim is not support. Applicant never teaches providing the adhesion promotion layer between the connector and passivation in a lamination direction. Applicant only shows the wherein the adhesion promotion pattern is disposed between the conductive connector and a periphery of the passivation layer in a schematic or plan view
b. As to claim 12, applicant does not teach wherein the first integrated circuit comprises a first conductive connector bonded to a second integrated circuit, the first conductive connector is disposed in a passivation layer, and the adhesion promotion pattern is disposed on and in direct contact with the passivation layer.
Recitation of the claim implies that the second is on top of the first die or stack which is not depicted it is noted that claim 12 is originally filed. This embodiment is not discussed or depicted. However, there is no way that wherein the first integrated circuit comprises a first conductive connector bonded to a second integrated circuit, the first conductive connector is disposed in a passivation layer, and the adhesion promotion pattern is disposed on and in direct contact with the passivation layer cannot be simultaneously true with a first integrated circuit bonded to the interposer…. wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer, and the adhesion promotion pattern is in direct contact with the underfill and the one of the first integrated circuit and the interposer
Claim 12 requires the adhesion to be between the first integrated circuit and second integrate circuit and in direct contact with the underfill between the first interposer. Claim 12 would require the adhesion film on a side opposite to the interposer or facing away.
c. As to claim 14, recitation of wherein a second integrated circuit comprises a second conductive connector bonded to the first integrated circuit, the second conductive connector is disposed in a dielectric layer, and the adhesion promotion pattern is disposed on and in direct contact with the dielectric layer cannot be done with first integrated circuit bonded to the interposer; an underfill between the interposer and the first integrated circuit; and an adhesion promotion pattern protruded from a surface of one of the first integrated circuit and the interposer, wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer, and the adhesion promotion pattern is in direct contact with the underfill and the one of the first integrated circuit and the interposer. Since the adhesion fil would protrude from the second circuit and neither the interposer or first circuit.
d. As to claim 21 Applicant does not have support for and the at least one adhesion promotion pattern surrounds a corner of the one of the first integrated circuit and the interposer. The adhesion layer is at the corner, it does not surround the corner in the traditional sense of surround, being on every side of the corner. The office will interpret surround to be at a corner region
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2, 6, 8-16 and 21-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 2, recitation of wherein a first surface of the adhesion promotion pattern is higher than a first surface of the conductive pad, and a second surface opposite to the first surface of the adhesion promotion pattern is lower than a first surface of the conductive pad.
It is unclear if these surfaces are the same or different.
As to claim 6, recitation of wherein the adhesion promotion pattern is disposed in a corner area of the semiconductor device is unclear since the scope of corner area is not adequately defined. It is unclear what a corner area is and is not.
As to claims 8 and 21, recites an adhesion promotion pattern protruded from a surface of one of the first integrated circuit and the interposer, wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer.
This is not proper Markush form it is unclear if applicant means selected from the group of or at least one of A or B. Further the use of and makes the claim unclear at least one of A and B is interpreted under superguide as both A and B. Applicant should clarify the use of the Markush recitation. The office will interpret the claim to mean an adhesion promotion pattern protruded at least one of a surface of one of the first integrated circuit or the interposer, wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer.
d. As to claim 12, There is no way that wherein the first integrated circuit comprises a first conductive connector bonded to a second integrated circuit, the first conductive connector is disposed in a passivation layer, and the adhesion promotion pattern is disposed on and in direct contact with the passivation layer cannot be simultaneously true with a first integrated circuit bonded to the interposer…. wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer, and the adhesion promotion pattern is in direct contact with the underfill and the one of the first integrated circuit and the interposer
Claim 12 requires the adhesion to be between the first integrated circuit and second integrate circuit and in direct contact with the underfill between the first interposer. Claim 12 would require the adhesion film on a side opposite to the interposer or facing away.
As to claim 14, recitation of wherein a second integrated circuit comprises a second conductive connector bonded to the first integrated circuit, the second conductive connector is disposed in a dielectric layer, and the adhesion promotion pattern is disposed on and in direct contact with the dielectric layer cannot be done with first integrated circuit bonded to the interposer; an underfill between the interposer and the first integrated circuit; and an adhesion promotion pattern protruded from a surface of one of the first integrated circuit and the interposer, wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer, and the adhesion promotion pattern is in direct contact with the underfill and the one of the first integrated circuit and the interposer. Since the adhesion film would protrude from the second circuit and neither the interposer or first circuit
As to claim 21, “surround a corner” is not clear since there is no embodiment that describes the adhesion promotion on every side of the corner
As to claim 23 Applicant has not established there are at least two sides.
Claims 12-14 are so unclear that an art rejection cannot be provided since it requires the adhesion pattern to be in too different mutually exclusive locations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11, 15-16, and 21-24 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Park 20240186277.
As to claim 1, Park teaches A semiconductor device (figure 4a-4c), comprising: a substrate (item 101 or 201); a passivation layer on the substrate (item 120 or items 211-212); a conductive pad in the passivation layer (item 140 or item 230); a conductive connector disposed on and electrically connected to the conductive pad (item 280); and an adhesion promotion pattern protruded from a surface of the passivation layer, wherein the adhesion promotion pattern is electrically isolated from the conductive connector (item 270 paragraph 44 and paragraph 20).
Paragraph 20:
Referring to FIGS. 1A and 1B, a semiconductor package 1000A according to an embodiment includes a plurality of semiconductor chips 100 and 200, a plurality of underfill layers 260, an encapsulant 290, and a plurality of insulating frames 270. FIG. 1B exemplarily illustrates how the plurality of semiconductor chips 200, the plurality of underfill layers 260, and the plurality of insulating frames 270 are disposed, in a plan view. Since they are insulating, they are at least electrically isolated from the connector.
Paragraph 44 states: The insulating frame 270 increases adhesion between the plurality of semiconductor chips 100 and 200 and the underfill layer 260. The terminal configuration of the plurality of semiconductor chips 200 is the front surface passivation layer 212, and the interface between the front surface passivation layer 212 and the underfill layer 260 is vulnerable to vapor pressure and thermal stress, so that interlayer delamination may occur. When the underfill layers 260 are reflowed through a thermal compression process, edge regions of the lower surfaces 200S of the semiconductor chips 200 are vulnerable to interlayer delamination. According to an embodiment of the present inventive concept, interface delamination between the semiconductor chip 200 and the underfill layer 260 is suppressed by locally disposing the insulating frame 270 in an area vulnerable to interlayer delamination. Therefore, the reliability of the semiconductor package is increased. In addition, the plurality of insulating frames 270 prevents the plurality of semiconductor chips 100 and 200 from being displaced when the plurality of semiconductor chips 100 and 200 are laminated on each other or may supplement a thickness tolerance of the plurality of semiconductor chips 100 and 200.
Thus, it serves the same claimed purpose.
b. As to claim 2, Park teaches (figure 4C) wherein a first surface of the adhesion promotion pattern is higher than a first surface of the conductive pad (the top of 270a , inContact with the 200s, is higher than the top of item 140), and a second surface opposite to the first surface of the adhesion promotion pattern is lower than the first surface of the conductive pad (the bottom of 270, part in contact with 120, is lower than the top of 140).
c. As to claim 3, Park teaches a polyimide (paragraph 43).
d. As to claim 4, Park teaches wherein the adhesion promotion pattern is disposed between the conductive connector and a periphery of the passivation layer in a plan view figure 4b and 4c it is between the connector region and an outer periphery of the passivation.
e. As to claim 5, Park teaches wherein the adhesion promotion pattern is in direct contact with the passivation layer (figures 4b and 4c).
f. As to claim 6, Park teaches wherein the adhesion promotion pattern is disposed in a corner region area of the semiconductor device It is at the corner of the active region area where the dies are placed.
g. As to claim 7, Park teaches wherein the promotion pattern comprises a plurality of adhesion promotion patterns and the conductive connector comprises a plurality of conductive connectors surrounded by the adhesion promotion patterns (figures 3 item 270 and figure 4 item 270 relative to item 280).
h. As to claim 8 and 21, Park teaches A semiconductor device, comprising: an interposer (item 100 figure 2 and 4); a first integrated circuit bonded to the interposer ( item 200a); an underfill between the interposer and the first integrated circuit (item 260a); and an adhesion promotion pattern protruded from a surface of one of the first integrated circuit and the interposer (figure 4b item 270 on the interposer paragraph 44: he insulating frame 270 increases adhesion between the plurality of semiconductor chips 100 and 200 and the underfill layer 260), wherein the adhesion promotion pattern is disposed between the first integrated circuit and the interposer (figure 4b), and the adhesion promotion pattern is in direct contact with the underfill and the one of the first integrated circuit and the interposer figure 4b in direct contact with 260 and 120). Park teaches the adhesion promotion pattern is at a corner region of the first circuit figures 3a and 3c-3d)
i. As to claim 9, Park teaches wherein the adhesion promotion pattern is disposed in a periphery area of the first integrated circuit (figure 2,4 and 3).
j. As to claim 10, Park teaches wherein the first integrated circuit comprises a plurality of first conductive connectors bonded to a second integrated circuit, the adhesion promotion pattern comprises a plurality of adhesion promotion patterns, and the adhesion promotion patterns are arranged along a periphery of the first integrated circuit to surround the first conductive connectors (figure 2 4 and 3a 3c and 3d relative to the connector items 280).
k. As to claim 11, Park teaches wherein the first integrated circuit comprises a first conductive connector (one of item 280), the interposer comprises a second conductive connector (a different one of the 280s), and the underfill surrounds the first conductive connector and the second conductive connector (item 260 relative to item 280s).
l. As to claim 15, Park teaches wherein the first integrated circuit comprises a plurality of first conductive connectors bonded to a second integrated circuit (items figures 2 4 280 between 200a and 200b), the adhesion promotion pattern comprises a plurality of adhesion promotion patterns (figure 3a-3d), and the adhesion promotion patterns are arranged along a periphery of the first integrated circuit to surround the first conductive connectors (figure 3a-3d and figure 4 and 2 items 270 are at the periphery of the connection elements and the bottommost 270 would surround the connection in the connection between 200a and 200b due to the TSV being directly above the corresponding ones of the interposer and 200a).
m. As to claim 16, Park teaches wherein the adhesion promotion pattern comprises a polymer (paragraph 43).
o. As to claim 22, Park teaches wherein the at least one adhesion promotion pattern comprises a plurality of separate patterns, and the separate patterns extend along at least two sides of the one of the first integrated circuit and the interposer (figure 3c).
p. As to claim 23, the claim does not state it extends from one side to another side.
Park teaches wherein the at least one adhesion promotion pattern is continuously extended along at least two sides, applicant does not set forth how far it is continuous, of the one of the first integrated circuit and the interposer (figure 3c has linear portion that continuously extends, and these are found on the four sides thus it meets the claim limitation).
q. As to claim 24, Park teaches wherein the at least one adhesion promotion pattern is ring-shaped (see e.g. figure 3c).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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