Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15, it is unclear how a length of the middle segment is greater than lengths of the first and second peripheral segments when the claim from which it depends requires the width of the middle segment be less than the widths of the first and second peripheral segments.
Election/Restrictions
Applicant’s election without traverse of claims 1-17 and 21-23 in the reply filed on 31 August 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-11 and 16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Klatt (US Pat. #8,193,603).
Regarding claim 1, Klatt teaches an integrated chip, comprising:
A substrate [fig. 9b, 110];
A first resistor layer overlying the substrate [fig. 9b, 142a]; and
An isolation structure contacting a first pair of opposing sidewalls of the first resistor layer, wherein the isolation structure comprises a body structure and a liner layer disposed on opposing sidewalls of the body structure [fig. 9b, 166b, made of liner 162 and body 164 shown in fig. 8b].
Regarding claim 2, Klatt discloses the integrated chip of claim 1, wherein the body structure comprises a conductive material [column 4, lines 63-67].
Regarding claim 3, Klatt teaches the integrated chip of claim 1, wherein the first pair of opposing sidewalls includes a first sidewall having a first length, wherein a first segment of the isolation structure continuously extends along the first sidewall and has a second length greater than the first length [fig. 9b, 166b extends along a first sidewall of 142a has a length greater than the first length of a first sidewall of 142a].
Regarding claim 4, Klatt discloses the integrated chip of claim 3, wherein a width of the first segment of the isolation structure is less than a distance between the first pair of opposing sidewalls of the first resistor layer [fig. 9b, the width of 166b where it extends along a sidewall of 142a is less than the width of 142a between the sidewalls].
Regarding claim 5, Klatt teaches the integrated chip of claim 1, wherein the first resistor layer comprises a second pair of opposing sidewalls arranged between the first pair of opposing sidewalls, wherein the isolation structure is disposed on the second pair of opposing sidewalls [fig. 9b, 142 has upper and lower sidewalls (sidewalls being interpreted as surfaces of the structure), 166b extends above the top and bottom sidewalls of 142a and is considered “on” the second sidewalls, alternatively 166c is part of the isolation structure and is disposed directly above the second pair of sidewalls of 142a].
Regarding claim 9, Klatt discloses the integrated chip of claim 1, further comprising: a second resistor layer overlying the substrate, wherein a segment of the isolation structure continuously extends from the first resistor layer to the second resistor layer, wherein a lateral distance between the first resistor layer and the second resistor layer is less than a maximum width of the segment of the isolation structure [fig.9b, second resistor layer 142c, 166b extends between 142a and 142c, 142a and c are on top of one another, making the lateral distance between them less than a width of 166b].
Regarding claim 10, Klatt teaches an integrated chip, comprising:
a first resistor layer overlying a substrate, wherein the first resistor layer comprises a middle segment, a first peripheral segment, and a second peripheral segment, wherein the middle segment extends between the first and second peripheral segments, wherein a width of the middle segment is less than widths of the first and second peripheral segments [see annotated fig. 9b below, middle segment between peripheral segments, the width of the middle segment is less than the peripheral segments];
a first contact structure on the first peripheral segment [fig. 9b, 126 on left side of image];
a second contact structure on the second peripheral segment [fig. 9b, 126 on right side of image]; and
an isolation structure abutting the first peripheral segment and the second peripheral segment [fig. 9b, 166b].
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Regarding claim 11, Klatt discloses the integrated chip of claim 10, wherein a width of a first isolation segment of the isolation structure along the first peripheral segment is less than a width of the first contact structure [fig. 9b, the width of 166b along the first peripheral segment is less than the width of 126].
Regarding claim 16, Klatt teaches the integrated chip of claim 10, wherein a width of the first contact structure is less than a width of the first peripheral segment and is greater than the width of the middle segment [fig. 9b, the width of 126 is less than the width of the peripheral segment, the middle segment can be reinterpreted so that the width of the middle segment is less than the width of 126].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Klatt as applied to claims 1-5, 9-11 and 16 above, and further in view of Johnson et al. (US Pat. #7,633,373)
Regarding claim 6, Klatt fails to teach a conductive via over the first resistor layer, wherein a top surface of the conductive via is coplanar with a top surface of the isolation structure. However, Johnsons teaches a resistor structure with isolation structure and conductive vias above the resistor, the conductive via is coplanar with a top surface of the isolation structure [fig. 23b, vias 336, isolation structure 324, resistor 234].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Johnson into the method of Klatt by forming a conductive via over the first resistor layer, wherein a top surface of the conductive via is coplanar with a top surface of the isolation structure. The ordinary artisan would have been motivated to modify Klatt in the manner set forth above for at least the purpose of utilizing known processes for reliably interconnecting to structures below.
Allowable Subject Matter
Claims 21-23 are allowed.
Claims 7, 8,12-14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 21, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach an isolation structure disposed in the second dielectric layer and extending through the resistive layer, wherein the isolation structure is spaced laterally between the resistor segment and the peripheral region of the resistive layer, wherein a top surface of the isolation structure is above a top surface of the pair of conductive structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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