DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the last limitation of claim 3 recites “wherein a resistivity of the semiconductor film is smaller than a resistivity of the third conductive film” despite the only mention of resistivity in Applicant’s specification being in paragraph [0253] which seemingly discloses the opposite of what is claimed here. For purposes of examination, this limitation will be interpreted as having a typo and thus reading ‘higher’ (given use of the word ‘lower’ in paragraph [0253]) instead of ‘smaller’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0025677 A1 to Yamazaki et al. (hereinafter “Yamazaki”).
Regarding claim 2, Yamazaki discloses a semiconductor device comprising a pixel (semiconductor device which may be LCD display having array of display pixels; abstract; Fig. 10A-10B; paragraphs [0005], [0015], [0214]), the pixel comprising:
a transistor;
a capacitor; and
a pixel electrode (each pixel comprising TFT 201, capacitor wiring layer 204, and pixel electrode in form of layers 255, 265; Fig. 16B; paragraphs [0271]-[0277]), wherein the transistor comprises:
a first conductive film functioning as a gate electrode;
a gate insulating film over the first conductive film;
a semiconductor film over the gate insulating film (bottom-gate structure with gate electrode 101 formed over substrate 100, gate insulating films 102a, 102b formed over gate electrode 101, and semiconductor layer 103 over films 102a, 102b; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]); and
a second conductive film over the semiconductor film, the second conductive film functioning as one of a source electrode and a drain electrode (source and drain electrodes 105a, 105b formed over layer 103; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]-[0087]), wherein the capacitor comprises:
a third conductive film;
a first insulating film over the third conductive film (wiring layer 204 comprising conductive material disposed above gate structure including electrode 101 and films 102a, 102b, where insulating layer 211 is disposed above layer 204; Figs. 1A-1B, 16A-16B; paragraphs [0094], [0271]-[0273]); and
a fourth conductive film over the first insulating film, wherein the fourth conductive film has a region functioning as the pixel electrode (electrode layer 255 disposed over layer 211, where layer 255 has region functioning as pixel electrode; Fig. 16B; paragraphs [0271]-[0277]), wherein the fourth conductive film is positioned over the second conductive film, wherein the fourth conductive film is electrically connected to the second conductive film (layer 255 positioned over and connected to electrodes 105a, 105b; Fig. 16B; paragraphs [0271]-[0277]), wherein the fourth conductive film has a region overlapping with the second conductive film through the first insulating film and a second insulating film (layer 255 overlaps with electrodes 105a, 105b in region where it is disposed through insulating layers 211, 212; Fig. 16B; paragraphs [0271]-[0277]), wherein the capacitor and the second insulating film do not overlap with each other (capacitor layer 204 does not overlap with layer 212; Fig. 16A), wherein the semiconductor film comprises indium, gallium, and zinc (semiconductor layer 103 may be made from IGZO; paragraphs [0126], [0271]), and wherein a carrier concentration of the semiconductor film is smaller than a carrier concentration of the third conductive film (capacitor layer 204 made from metal conductor having higher carrier concentration than layer 103; paragraphs [0092], [0094], [0113]).
Yamazaki fails to explicitly disclose a third conductive film over the gate insulating film which comprises indium, gallium, and zinc while having a hydrogen concentration larger than the semiconductor film.
However, Yamazaki already discloses buffer layers 104a, 104b (conductive film) formed over gate insulating layers 102a, 102b with insulating layer 211 disposed thereover (see Fig. 16B), which may be made from material including indium, gallium, and zinc (see paragraphs [0124]-[0125]), where buffer layers 104a, 104b (conductive film) exhibit higher carrier concentration than semiconductor layer 103 (semiconductor film) in order to form good ohmic contact with source/drain electrodes 105a, 105b (see abstract; paragraphs [0085], [0126]). Further, Yamazaki explicitly discusses hydrogen concentrations of related device materials (see paragraph [0086]) and the effect of hydrogen implantation on the performance of the various TFT films (see paragraph [0198]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yamazaki, in view of the related disclosure therein, with such a third conductive film to potentially provide a layer with higher conductivity via controlled hydrogen doping for good ohmic contact between adjacent layers, material compatibility with the IGZO channel, and utility as a lower electrode when over the insulating film. Further, providing such a third conductive film in the same positional relationship already shown for the conductive barrier layers (which have the claimed material and electrical properties) amounts to simply repeating/duplicating an already-disclosed structural element in an orientation that the specification already contemplates for related purposes and, therefore, is considered mere duplication of parts under MPEP 2144.04(VI)(B).
Regarding claim 3, as best understood, Yamazaki discloses a semiconductor device comprising a pixel (semiconductor device which may be LCD display having array of display pixels; abstract; Fig. 10A-10B; paragraphs [0005], [0015], [0214]), the pixel comprising:
a transistor;
a capacitor; and
a pixel electrode (each pixel comprising TFT 201, capacitor wiring layer 204, and pixel electrode in form of layers 255, 265; Fig. 16B; paragraphs [0271]-[0277]), wherein the transistor comprises:
a first conductive film functioning as a gate electrode;
a gate insulating film over the first conductive film;
a semiconductor film over the gate insulating film (bottom-gate structure with gate electrode 101 formed over substrate 100, gate insulating films 102a, 102b formed over gate electrode 101, and semiconductor layer 103 over films 102a, 102b; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]); and
a second conductive film over the semiconductor film, the second conductive film functioning as one of a source electrode and a drain electrode (source and drain electrodes 105a, 105b formed over layer 103; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]-[0087]), wherein the capacitor comprises:
a third conductive film;
a first insulating film over the third conductive film (wiring layer 204 comprising conductive material disposed above gate structure including electrode 101 and films 102a, 102b, where insulating layer 211 is disposed above layer 204; Figs. 1A-1B, 16A-16B; paragraphs [0094], [0271]-[0273]); and
a fourth conductive film over the first insulating film, wherein the fourth conductive film has a region functioning as the pixel electrode (electrode layer 255 disposed over layer 211, where layer 255 has region functioning as pixel electrode; Fig. 16B; paragraphs [0271]-[0277]), wherein the fourth conductive film is positioned over the second conductive film, wherein the fourth conductive film is electrically connected to the second conductive film (layer 255 positioned over and connected to electrodes 105a, 105b; Fig. 16B; paragraphs [0271]-[0277]), wherein the fourth conductive film has a region overlapping with the second conductive film through the first insulating film and a second insulating film (layer 255 overlaps with electrodes 105a, 105b in region where it is disposed through insulating layers 211, 212; Fig. 16B; paragraphs [0271]-[0277]), wherein the capacitor and the second insulating film do not overlap with each other (capacitor layer 204 does not overlap with layer 212; Fig. 16A), wherein the semiconductor film comprises indium, gallium, and zinc (semiconductor layer 103 may be made from IGZO; paragraphs [0126], [0271]), and wherein a resistivity of the semiconductor film is higher than a resistivity of the third conductive film (resistivity of semiconductor layer 103 is larger than that of capacitive layer 204; paragraphs [0094], [0271]-[0273]).
Yamazaki fails to explicitly disclose a third conductive film over the gate insulating film which comprises indium, gallium.
However, Yamazaki already discloses buffer layers 104a, 104b (conductive film) formed over gate insulating layers 102a, 102b with insulating layer 211 disposed thereover (see Fig. 16B), which may be made from material including indium, gallium, and zinc (see paragraphs [0124]-[0125]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yamazaki, in view of the related disclosure therein, with such a third conductive film to potentially provide a layer with material compatibility with the IGZO channel and utility as a lower electrode when over the insulating film. Further, providing such a third conductive film in the same positional relationship already shown for the conductive barrier layers (which have the claimed material and electrical properties) amounts to simply repeating/duplicating an already-disclosed structural element in an orientation that the specification already contemplates for related purposes and, therefore, is considered mere duplication of parts under MPEP 2144.04(VI)(B).
Regarding claim 4, Yamazaki discloses a semiconductor device comprising a pixel (semiconductor device which may be LCD display having array of display pixels; abstract; Fig. 10A-10B; paragraphs [0005], [0015], [0214]), the pixel comprising:
a transistor;
a capacitor; and
a pixel electrode (each pixel comprising TFT 201, capacitor wiring layer 204, and pixel electrode in form of layers 255, 265; Fig. 16B; paragraphs [0271]-[0277]), wherein the transistor comprises:
a first conductive film functioning as a gate electrode;
a gate insulating film over the first conductive film;
a semiconductor film over the gate insulating film (bottom-gate structure with gate electrode 101 formed over substrate 100, gate insulating films 102a, 102b formed over gate electrode 101, and semiconductor layer 103 over films 102a, 102b; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]); and
a second conductive film over the semiconductor film, the second conductive film functioning as one of a source electrode and a drain electrode (source and drain electrodes 105a, 105b formed over layer 103; Figs. 1A-1B; paragraphs [0024], [0026], [0040], [0084]-[0087]), wherein the capacitor comprises:
a third conductive film;
a first insulating film over the third conductive film (wiring layer 204 comprising conductive material disposed above gate structure including electrode 101 and films 102a, 102b, where insulating layer 211 is disposed above layer 204; Figs. 1A-1B, 16A-16B; paragraphs [0094], [0271]-[0273]); and
a fourth conductive film over the first insulating film, wherein the fourth conductive film has a region functioning as the pixel electrode (electrode layer 255 disposed over layer 211, where layer 255 has region functioning as pixel electrode; Fig. 16B; paragraphs [0271]-[0277]), wherein the fourth conductive film is positioned over the second conductive film (layer 255 positioned over and connected to electrodes 105a, 105b; Fig. 16B; paragraphs [0271]-[0277]).
Yamazaki fails to explicitly disclose a third conductive film over the gate insulating film.
However, Yamazaki already discloses buffer layers 104a, 104b (conductive film) formed over gate insulating layers 102a, 102b with insulating layer 211 disposed thereover (see Fig. 16B).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Yamazaki, in view of the related disclosure therein, with such a third conductive film to potentially provide a layer with utility as a lower electrode when over the insulating film and reduced parasitic effects or electric field concentration at interfaces. Further, providing such a third conductive film in the same positional relationship already shown for the conductive barrier layers (which have the claimed material and electrical properties) amounts to simply repeating/duplicating an already-disclosed structural element in an orientation that the specification already contemplates for related purposes and, therefore, is considered mere duplication of parts under MPEP 2144.04(VI)(B).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2004/0263708 A1 to Cho et al., US 2011/0127520 A1 to You, and US 2011/0183463 A1 to Kim et al. which each disclose semiconductor devices having related pixel transistor arrangements.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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