DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hamada (U.S. Publication No. 2017/0110159).
Regarding claim 1, Hamada teaches a method for automatically generating chip identifier for semiconductor dies in a stacked structure, comprising:
obtaining a first semiconductor die (Fig. 12, first die 4a) and a second semiconductor die (2b), wherein the first semiconductor die and the second semiconductor die comprise a first identifier generation circuit (10) and a second identifier generation circuit (14), respectively;0
forming a stacked structure by stacking the second semiconductor die on the first semiconductor die (Fig. 12), wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit (Fig. 12); and
generating a first chip identifier and a second chip identifier for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively, wherein the second chip identifier is a bit-shifted value of the first chip identifier (see Fig. 13).
Regarding claim 2, Hamada teaches the method of Claim 1, further comprising: electrically connecting the first identifier generation circuit to the second identifier generation circuit through a plurality of through-silicon vias within the first semiconductor die (see paragraph [0121]).
Regarding claim 3, Hamada teaches the method of Claim 1, further comprising: generating the first chip identifier using a preset value in response to the first semiconductor die being a bottom die within the stacked structure (see paragraph [0069], when it is bottom die, the input data is ground, and therefore no bit shift occurs).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hamada in view of Morohashi et al. (U.S. Publication No. 2018/0254074).
Regarding claim 6, Hamada teaches the method of Claim 1, further comprising: utilizing the first identifier generation circuit and the second identifier generation circuit to transmit the first chip identifier and the second chip identifier to a first decoder circuit and a second decoder circuit disposed on the first semiconductor die and the second semiconductor die, respectively.
However, Morohashi teaches that the chips have decoder circuits to receive the chip ID (Morohashi Fig. 7, decoder 706 receives chip ID 716). It would have been obvious to a person of skill in the art at the time of the effective filing date that the chips could have had decoder circuits because Morohashi teaches that this allows for decoding of various command signals for the memory (Morohashi paragraph [0049]).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4-5, the prior art, alone or in combination, fails to teach or suggest wherein a most significant bit of the preset value is 1, and each bit other than the most significant bit of the preset value is 0, in combination with the other limitations of the claims from which claim 4 depends.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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