Prosecution Insights
Last updated: August 17, 2026
Application No. 18/664,622

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF

Non-Final OA §103§112
Filed
May 15, 2024
Priority
Apr 15, 2024 — divisional of 18/635,407
Examiner
DANG, PHUC T
Art Unit
Tech Center
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1748 granted / 1832 resolved
+35.4% vs TC avg
Minimal +1% lift
Without
With
+1.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
31 currently pending
Career history
1851
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
60.8%
+20.8% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1832 resolved cases

Office Action

§103 §112
DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Cross-Reference to Related Applications 2. This application is a DIV of 18/635,407 04/15/2024. Oath/Declaration 3. The oath/declaration filed on 05/15/2024 is acceptable. Information Disclosure Statement 4. The office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 06/10/2025 and 11/26/2025. Specification 5. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01). A title such as -- METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE – or is suggested by the applicant. Note that the claims are directed to a method of making a semiconductor device instead of a semiconductor device. The specification needs to be updated. Claim Rejections-35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 6. Claim 9 is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 9 recites the limitation "the insulating layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 7. Claims 1-3 and 5-11 are rejected under 35 U.S.C. 103(a) as being unpatentable over ZHUANG Y (CN-117373918-A) in view of CAI Z (CN-113517290-A). Regarding claim 1, ZHUANG Y discloses a method for manufacturing a semiconductor structure, comprising: forming a silicon portion (12), a plurality of dielectric portions (131) and a plurality of oxide portions (51) in a substrate (11); forming at least one first trench (45, Fig. 24) in the silicon portion (12) of the substrate (11), forming a word line (521) in the first trench (45); forming a first dielectric layer (53, Fig. 31) over the substrate (11) and covering the word line (521); and forming a second dielectric layer (54, Fig. 31) to cover the first dielectric layer (53) (Figs. 23-31 and English Text). ZHUANG Y discloses the features of the claimed invention as discussed above, but does not disclose wherein the first trench has a W-shaped contour. CAI Z, however, discloses wherein the first trench (120) has a W-shaped contour (Figs. 7A-7B and English Text). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of ZHUANG Y to provide wherein the first trench has a W-shaped contour as taught by CAI Z for a purpose of reducing the defect density (defect density) and reducing the electric field concentration in the operation period of the element. ZHUANG Y and CAI Z disclose forming a plurality of first impurity regions (130) and a plurality of second impurity regions (140) in the substrate (110), wherein each of the second impurity regions (140) is disposed between a pair of legs of the word line (174) (Fig. 1 and English Text in CAI Z). Regarding claim 2, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein the substrate (110) and the first impurity region (130) have a same conductivity type (claim 6 in CAI Z). Regarding claim 3, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein the second impurity region (140, P-type) and the first impurity region (130, N-type) have different conductivity types (Fig. 1 in CAI Z). Regarding claim 5, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein the word line (174) further comprises bases (1742) disposed on the legs (1744) of the word line (174) (Fig. 1 in CAI Z). Regarding claim 6, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein a width of the leg of the word line (174) gradually decreases at positions of increasing distance from a top surface of the substrate (110) (Fig. 1 in CAI Z). Regarding claim 7, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein a width of the second impurity region (140) gradually increases at positions of increasing distance from the base (1742) of the word line (174) (Fig. 1 in CAI Z). Regarding claim 8, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein a top surface of the word line (521/522) is at a same level as a designed top surface (Fig. 29). Regarding claim 9, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses further comprising: forming a plurality of second openings (44) in an insulating layer (141); forming a plurality of second trenches (46) in the substrate (11) through the plurality of second openings; and forming a plurality of contacts (522) in the second trenches (46) (Figs. 26-27). Regarding claim 10, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein a depth of the second trench (46) is greater than a depth of the first trench (45) (Fig. 23). Regarding claim 11, ZHUANG Y and CAI Z (citations to ZHUANG Y unless otherwise noted) discloses wherein a height of the contact (522) is greater than a height of the word line (521) (Fig. 29). 8. Claim 4 is rejected under 35 U.S.C. 103(a) as being unpatentable over ZHUANG Y and CAI Z in view of HUANG (U.S. Publication No. 2021/0242211 A1). Regarding claim 4, ZHUANG Y and CAI Z discloses the features of the claimed invention as discussed above, but does not disclose further comprising, before the formation of the word line: forming an isolation film lining the first trench; and conformally forming a diffusion barrier film on the isolation film, wherein the word line is formed on the diffusion barrier film and fills the first trench. HUANG, however, discloses further comprising, before the formation of the word line (144): forming an isolation film (124) lining the first trench (112); and conformally forming a diffusion barrier film (134) on the isolation film (124), wherein the word line (144) is formed on the diffusion barrier film (134) and fills the first trench (112) (Fig. 1B and para [0044]-[0045]). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of ZHUANG Y and CAI Z to provide further comprising, before the formation of the word line: forming an isolation film lining the first trench; and conformally forming a diffusion barrier film on the isolation film, wherein the word line is formed on the diffusion barrier film and fills the first trench as taught by HUANG for a purpose of preventing the word lines from flaking or spalling from the isolation film. Cited Prior Arts 9. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. CHOI Z (CN-112490181-A) discloses a method for manufacturing a semiconductor structure, comprising the first trench 131 the remaining portion (i.e., the receiving portion 130) filling the conductive material 70, and the second trench 133 filled with conductive material 70, the conductive material 70 also covers the barrier layer 50 away from the surface of the substrate 10 (Fig. 2D and English Text). Conclusion 10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHUC T DANG/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 15, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+1.3%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1832 resolved cases by this examiner. Grant probability derived from career allowance rate.

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