DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on August 5th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 4-10, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 4-10, regarding the newly amended claim limitations:
The Examiner notes a new combination has been presented in light of the newly presented amendments such that arguments directed solely to the previously presented rejections are now moot.
With regards to the Applicant’s arguments directed towards Lee, the Examiner notes that Lee is not relied upon for the limitations which have already been disclosed by Kim. It is also shown in Lee that a top surface structure may alternatively be modified such that the combination is simple substitution to obtain predictable results.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites in line 2 “a conductive pattern , a conductive pattern , and a bit line capping”.
There are two newly introduced “a conductive pattern” with the same language for which it is indefinite as to the relationship between them.
For the purposes of compact prosecution the interpretation will be taken that the two conductive patterns are different from each other.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-12 are rejected under 35 U.S.C. 103 as obvious over Kim (US 2018/0040560 A1), hereinafter as K1 in view of Lee et al. (US 2024/0349491 A1), hereinafter as L1
7. Regarding Claim 1, K1, L1 discloses a semiconductor device (see in particular Figs. 1A-C, 2A-B, and [0010] “semiconductor memory device”), comprising:
a substrate (element 100, see [0021] “substrate 100”); and
a first bit line structure (first element BLS, DC, SS over element 1a, see [0026] “bit line structures BLS … bit line contact pattern DC” and [0038] “spacer structure SS”) disposed over the substrate;
wherein the first bit line structure comprises a core structure (element BLS) and a first spacer (element 131, see [0039] “first and second spacers 131 and 135”) continuously disposed on a sidewall of the core structure (see Fig. 2B) and fill a space between the first bit line structure and the substrate (space between an upper portion of element 1a and element BLS, SS in a diagonally aligned direction in the same manner as the Applicant’s invention; furthermore, the manner in which the claim is currently recited is broad such that it does not require a particular direction),
wherein a bottom surface of the core structure is aligned with a bottom surface of the first spacer (see Fig. 2B).
K1 does not explicitly disclose while a top surface of the core structure is aligned with a top surface of the first spacer.
L1 discloses while a top surface of the core structure is aligned with a top surface of the first spacer (see Fig. 12B top surface of core structure element DC, BL, 350 is aligned with a top surface of the first spacer element LS, see [0033-0035]).
The top shape of the core structure with respect to the first spacer as taught by L1 is incorporated as a top shape of the core structure with respect to the first spacer of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known top shape of the core structure with respect to the first spacer for another for which alternative shapes are presented to be selectable to obtain predictable results (see L1 Fig. 3A-B versus 12A-B the top surface shape may be non-planar versus planar)
8. Regarding Claim 2, K1, L1 discloses the semiconductor device of claim 1, wherein the first spacer extends between the core structure and the substrate (see K1 Fig. 2B extends in the space between an upper portion of element 1a of the substrate and element BLS, SS in a diagonally aligned direction).
9. Regarding Claim 3, K1, L1 discloses the semiconductor device of claim 1, wherein the first bit line structure contacts a first doped region (see K1 element 1a, see [0025] “first and second impurity regions 1a and 1b”) in the substrate.
10. Regarding Claim 4, K1, L1 discloses the semiconductor device of claim 1.
K1, L1 as previously combined do not disclose wherein the first spacer includes a carbon-containing material.
L1 discloses wherein the first spacer includes a carbon-containing material (see Fig. 3A first spacer element LS see [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”, the second spacer element INS see [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)”, and the third spacer element OUS see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”).
The first spacer material as taught by L1 is incorporated as the first spacer material of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known first spacer material in a similar device for another to obtain predictable results (see L1 Fig. 3A and [0034, 0048, 0052] each of the spacers are described with a list of material which can be selected and substituted).
11. Regarding Claim 5, K1, L1 discloses the semiconductor device of claim 1, further comprising (see K1): a storage node contact (element 153, see [0031] “contact conductive pad 153”; also see electrical connection above through element CPS to the data storage pattern element DSP) disposed adjacent to the first bit line structure (see Fig. 1B, 2B).
12. Regarding Claim 6, K1, L1 discloses the semiconductor device of claim 5, wherein the first spacer contacts the storage node contact (see K1 Fig. 2B).
13. Regarding Claim 7, K1, L1 discloses the semiconductor device of claim 5, wherein the storage node contact contacts a second doped region (see K1 element 1b, see [0025] “second impurity region 1b”) in the substrate.
14. Regarding Claim 8, K1, L1 discloses the semiconductor device of claim 5, wherein a bottom surface of the first bit line structure is lower than the storage node contact with respect to the substrate (see K1 bottom surface of BLS, DC, SS is lower than element 153).
15. Regarding Claim 9, K1, L1 discloses the semiconductor device of claim 1, further comprising: a second bit line structure (see K1 second element BSL, SS immediately adjacent to the first bit line structure over element 101, see Fig. 1B) disposed over the substrate, wherein the first spacer extends between the core structure and the second bit line structure (see K1 Fig. 1B).
16. Regarding Claim 10, K1, L1 discloses the semiconductor device of claim 9, wherein the second bit line structure is spaced apart from the substrate by an interlayer (see K1 element 110, see [0032] “insulating interlayer 110”).
17. Regarding Claim 11, K1, L1 discloses the semiconductor device of claim 1.
K1, L1 as previously combined do not explicitly disclose wherein the first bit line structure has a second spacer continuously disposed over the first spacer, wherein the top surface of the core structure, the top surface of the first spacer, and a top surface of the second spacer are aligned with each other.
L1 discloses wherein the first bit line structure has a second spacer continuously disposed over the first spacer (see Fig. 3A first spacer element LS see [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”, and second spacer element INS see [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)” where element INS is continuously disposed over element LS, and the third spacer element OUS see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”), wherein the top surface of the core structure, the top surface of the first spacer, and a top surface of the second spacer are aligned with each other (see Fig. 3A).
The bit line multilayer spacer as taught by L1 is incorporated as the bit line multilayer spacer of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bit line multilayer spacer material in a similar device for another to obtain predictable results (see L1 Fig. 3A and [0034, 0048, 0052] each of the spacers are described with a list of material which can be selected and substituted).
18. Regarding Claim 12, K1, L1 disclose the semiconductor device of claim 11, wherein the second spacer includes an oxygen-containing material (see L1 [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)”).
19. Regarding Claim 13, K1, L1 disclose the semiconductor device of claim 1, wherein the substrate has a recess region (see K1 region above the top surface of element 1a) recessed from a top surface of the substrate, wherein the recess region has a bottom surface and a sidewall extended from the bottom surface of the recess region to the top surface of the substrate (see K1 Fig. 1B), wherein the bottom surface of the core structure and the bottom surface of the first spacer are disposed on and in direct contact with the bottom surface of the recess region (see K1 Fig. 1B recess region directly above element 1a).
20. Regarding Claim 14, K1, L1 disclose the semiconductor device of claim 13, wherein the first spacer is fully filled into a space between the core structure and the sidewall of the recess region (see K1 Fig. 1B, 2B), such that the first spacer is in direct contact with the sidewall of the core structure and the sidewall of the recess region (see K1 Fig. 1B, 2B).
21. Regarding Claim 15, K1, L1 disclose the semiconductor device of claim 14, wherein the sidewall of the recess region is inclined with respect to the top surface of the substrate (see K1 Fig. 1B, 2B).
22. Regarding Claim 16, K1, L1 disclose the semiconductor device of claim 13, wherein the core structure comprises a bit line contact (see K1 element DC), a conductive pattern (see K1 element 122, see [0026] “silicide pattern 122”), a conductive pattern (see K1 element 123, see [0026] “a metal pattern 123”), and a bit line capping pattern (element 125, see [0026] “hard mask pattern 125”) sequentially stacked on the bottom surface of the recess region (see K1 Fig. 1B, 2B);
wherein a bottom surface of the bit line contact is aligned with the bottom surface of the first spacer while a top surface of the bit line capping pattern is aligned with the top surface of the first spacer (see K1 Fig. 1B,2B and L1 Fig. 12B).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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