DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the first bit line structure has a first spacer continuously disposed on a sidewall of the first bit line structure and fill a space between the first bit line structure and the substrate”.
The first spacer is part of the first bit line structure but is also required to be between the first bit line structure and the substrate – there is a conflict between the first spacer being a part of the first bit line and then the first spacer being separate from the first bit line.
All claims depending on the current claim incorporate the same issues.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-3 and 5-10 are rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Kim (US 2018/0040560 A1), hereinafter as K1
5. Regarding Claim 1, K1 discloses a semiconductor device (see in particular Figs. 1A-C, 2A-B, and [0010] “semiconductor memory device”), comprising:
a substrate (element 100, see [0021] “substrate 100”); and
a first bit line structure (element BLS, SS, see [0026] “bit line structures BLS … bit line contact pattern DC” and [0038] “spacer structure SS”) disposed over the substrate;
wherein the first bit line structure has a first spacer (element 131, see [0039] “first and second spacers 131 and 135”) continuously disposed on a sidewall of the first bit line structure (see Fig. 2B) and fill a space between the first bit line structure and the substrate (space between an upper portion of element 1a and element BLS, SS in a diagonally aligned direction in the same manner as the Applicant’s invention; furthermore, the manner in which the claim is currently recited is broad such that it does not require a particular direction).
6. Regarding Claim 2, K1 discloses the semiconductor device of claim 1, wherein the first spacer extends between the first bit line structure and the substrate (see Fig. 2B extends in the space between an upper portion of element 1a of the substrate and element BLS, SS in a diagonally aligned direction).
7. Regarding Claim 3, K1 discloses the semiconductor device of claim 1, wherein the first bit line structure contacts a first doped region (element 1a, see [0025] “first and second impurity regions 1a and 1b”) in the substrate.
8. Regarding Claim 5, K1 discloses the semiconductor device of claim 1, further comprising: a storage node contact (element 153, see [0031] “contact conductive pad 153”; also see electrical connection above through element CPS to the data storage pattern element DSP) disposed adjacent to the first bit line structure (see Fig. 1B, 2B).
9. Regarding Claim 6, K1 discloses the semiconductor device of claim 5, wherein the first spacer contacts the storage node contact (see Fig. 2B).
10. Regarding Claim 7, K1 discloses the semiconductor device of claim 5, wherein the storage node contact contacts a second doped region (element 1b, see [0025] “second impurity region 1b”) in the substrate.
11. Regarding Claim 8, K1 discloses the semiconductor device of claim 5, wherein a bottom surface of the first bit line structure is lower than the storage node contact with respect to the substrate (bottom surface of BLS, SS is lower than element 153).
12. Regarding Claim 9, K1 discloses the semiconductor device of claim 1, further comprising: a second bit line structure (second element BSL, SS immediately adjacent to the first bit line structure, see Fig. 1B) disposed over the substrate, wherein the first spacer extends between the first bit line structure and the second bit line structure (see Fig. 1B).
13. Regarding Claim 10, K1 discloses the semiconductor device of claim 9, wherein the second bit line structure is spaced apart from the substrate by an interlayer element 110, see [0032] “insulating interlayer 110”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claims 4 and 11-12 are rejected under 35 U.S.C. 103 as obvious over Kim (US 2018/0040560 A1), hereinafter as K1 in view of Lee et al. (US 2024/0349491 A1), hereinafter as L1
15. Regarding Claim 4, K1 discloses the semiconductor device of claim 1.
K1 does not disclose wherein the first spacer includes a carbon-containing material.
L1 discloses wherein the first spacer includes a carbon-containing material (see Fig. 3A first spacer element LS see [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”, the second spacer element INS see [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)”, and the third spacer element OUS see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”).
The first spacer material as taught by L1 is incorporated as the first spacer material of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known first spacer material in a similar device for another to obtain predictable results (see L1 Fig. 3A and [0034, 0048, 0052] each of the spacers are described with a list of material which can be selected and substituted).
16. Regarding Claim 11, K1 discloses the semiconductor device of claim 1.
K1 does not explicitly disclose wherein the first bit line structure has a second spacer continuously disposed over the first spacer.
L1 discloses wherein the first bit line structure has a second spacer continuously disposed over the first spacer (see Fig. 3A first spacer element LS see [0034] “The line spacer LS may be formed of or include at least one of … silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN)”, and second spacer element INS see [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)” where element INS is continuously disposed over element LS, and the third spacer element OUS see [0052] “The outer spacer OUS may be formed of or include at least one of … silicon nitride (SiN)”).
The bit line multilayer spacer as taught by L1 is incorporated as the bit line multilayer spacer of K1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of L1 with K1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bit line multilayer spacer material in a similar device for another to obtain predictable results (see L1 Fig. 3A and [0034, 0048, 0052] each of the spacers are described with a list of material which can be selected and substituted).
17. Regarding Claim 12, K1, L1 disclose the semiconductor device of claim 11, wherein the second spacer includes an oxygen-containing material (see L1 [0048] “The inner spacer INS may be formed of or include at least one of silicon oxide (SiO2)”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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