DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Lisiansky et al. (US 2009/0181530) and Agarwal (US 2001/0015453).
In reference to claim 1, Bohr (US 2013/0267070), hereafter “Bohr,” discloses a device, with reference to Figure 8, comprising:
a first gate electrode, the first gate electrode comprising:
a first high-k dielectric layer, 131;
a first p-type work function tuning metal 162 contacting the first high-k dielectric layer, paragraph 47; and
a first conductive material 171 over the first p-type work function tuning metal, paragraph 48;
a second gate electrode, the second gate electrode comprising:
a second high-k dielectric layer, 131;
a first n-type work function tuning metal 161 contacting the second high-k dielectric layer, paragraph 46;
a second p-type work function tuning metal 162 contacting the first n-type work function tuning metal, paragraph 47; and
a second conductive material 171 over the second p-type work function tuning metal, paragraph 48.
Bohr does not disclose the crystallinity of the first high-k dielectric layer and the second high-k dielectric layer is higher than 70 percent.
Lisiansky et al. (US 2009/0181530), hereafter “Lisiansky,” discloses an analogous semiconductor device including teaching a high-k dielectric layer for CMOS transistors (721, 712 in Figure 7D, for example) that is crystalline, paragraph 47, and Agarwal teaches high-k dielectric films considered to be crystalline when they have greater than or equal to about 70% crystallinity, paragraph 22.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the crystallinity of the first high-k dielectric layer and the second high-k dielectric layer to be higher than 70 percent. One would have been motivated to do so in order to provide a dielectric with low leakage current, paragraph 51.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Lisiansky et al. (US 2009/0181530) and Agarwal (US 2001/0015453) as applied to claim 1 above and further in view of Li (US 2018/0151575).
In reference to claim 2, Bohr does not disclose a third gate electrode, the third gate electrode comprising: a third high-k dielectric layer; a third p-type work function tuning metal contacting the third high-k dielectric layer; a fourth p-type work function tuning metal contacting the third p-type work function tuning metal; and a third conductive material over the fourth p-type work function tuning metal
Li (US 2018/0151575), hereafter “Li,” discloses an analogous semiconductor device including teaching a third gate electrode, region II of Figure 13, for example, the third gate electrode comprising: a third high-k dielectric layer 102, paragraph 51; a third p-type work function tuning metal 320 contacting the third high-k dielectric layer, paragraph 76; a fourth p-type work function tuning metal 330 contacting the third p-type work function tuning metal, paragraph 93; and a third conductive material 500 over the fourth p-type work function tuning metal, paragraph 113.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the device to comprise a third gate electrode, the third gate electrode comprising: a third high-k dielectric layer; a third p-type work function tuning metal contacting the third high-k dielectric layer; a fourth p-type work function tuning metal contacting the third p-type work function tuning metal; and a third conductive material over the fourth p-type work function tuning metal.
One would have been motivated to do so in order to incorporate multiple transistors of different electrical characteristics, such as threshold voltage, in the same device, paragraph 6.
In reference to claim 3, Bohr teaches the first and the second p-type work function tuning metal comprises the same material, 162 in Figure 7, paragraph 47.
Li further teaches the first, the second, 310, the third, 320, and the fourth, 330 p-type work function tuning metal comprises the same material, paragraphs 77 and 94.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first, the second, the third, and the fourth p-type work function tuning metal to comprise the same material. One would have been motivated to do so in order to provide improved process compatibility across forming the respective tuning metals, paragraph 77.
In reference to claim 4, Li discloses the first, the second, the third, and the fourth p-type work function tuning metal comprises titanium nitride, paragraphs 77 and 94.
Bohr does not disclose the first n-type work function tuning metal comprises titanium aluminum nitride.
Li further teaches a first n-type work function tuning metal 400 comprises titanium aluminum nitride, paragraph 111.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first n-type work function tuning metal to comprise titanium aluminum nitride.
One would have been motivated to do so in order to set a desired work function for the transistors, paragraphs 63 and 111.
In reference to claim 5, Li discloses a combined thickness of the third p-type work function tuning metal and the fourth p-type work function tuning metal, (10-30 Å, respectively, and therefore a combined 20-60 Å) paragraphs 78 and 98, is larger than a thickness of the first p-type work function tuning metal, (15-35 Å) paragraph 65.
Claims 6, 8-10, 13, 14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Park et al. (US 2023/0020176).
In reference to claim 6, Bohr (US 2013/0267070), hereafter “Bohr,” discloses a device, with reference to Figure 8, comprising:
a first gate electrode, the first gate electrode comprising:
a high-k dielectric layer, 131 that comprises a first material;
a first n-type work function tuning metal 161 contacting the high-k dielectric layer, paragraph 46;
a second p-type work function tuning metal 162 contacting the first n-type work function tuning metal, paragraph 47; and
a first conductive material 171 over the second p-type work function tuning metal, paragraph 48.
Bohr does not disclose a second high-k dielectric layer over and in contact with the first high-k dielectric layer, wherein the second high-k dielectric layer comprises a second material that is different from the first material, and wherein a thickness of the second high-k dielectric layer is smaller than a thickness of the first high-k dielectric layer.
Park et al. (US 2023/0020176), hereafter “Park,” discloses an analogous device including teaching a first gate electrode comprising:
a high-k dielectric layer, HK1 in Figure 3A, that comprises a first material; and
a second high-k dielectric layer, HK2, over and in contact with the first high-k dielectric layer, wherein the second high-k dielectric layer comprises a second material that is different from the first material, paragraph 84, and wherein a thickness of the second high-k dielectric layer is smaller than a thickness of the first high-k dielectric layer, paragraph 95.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a second high-k dielectric layer to be over and in contact with the first high-k dielectric layer, wherein the second high-k dielectric layer comprises a second material that is different from the first material, and wherein a thickness of the second high-k dielectric layer is smaller than a thickness of the first high-k dielectric layer.
One would have been motivated to do so in order to provide a thin gate dielectric with good reliability and a high breakdown voltage, paragraph 89.
In reference to claim 8, Park discloses the thickness of the first high-k dielectric layer is in a range from 1 nm to 4 nm, and the thickness of the second high-k dielectric layer is in a range from 1 nm to 2 nm, paragraph 95.
In reference to claim 9, Bohr discloses a second gate electrode, 172 in Figure 8.
Bohr does not disclose the second gate electrode comprising: a third high-k dielectric layer that comprises the first material; and a fourth high-k dielectric layer over and in contact with the third high-k dielectric layer, wherein the fourth high-k dielectric layer comprises the second material.
Park teaches a second gate electrode, GE1 of region PR1 in Figures 2, the second gate electrode comprising: a third high-k dielectric layer HK1, that comprises the first material; and a fourth high-k dielectric layer HK2 over and in contact with the third high-k dielectric layer, wherein the fourth high-k dielectric layer comprises the second material, paragraphs 47 and 81. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second gate electrode to comprise: a third high-k dielectric layer that comprises the first material; and a fourth high-k dielectric layer over and in contact with the third high-k dielectric layer, wherein the fourth high-k dielectric layer comprises the second material.
One would have been motivated to do so in order to concurrently form transistors of different conductivity and characteristics, paragraphs 26 and 157.
In reference to claim 10, Bohr in view of Park discloses the second gate electrode further comprises: a third p-type work function tuning metal, 162 in Figure 8 of Bohr, contacting the fourth high-k dielectric layer 131; and a second conductive material 172 over the third p-type work function tuning metal, paragraph 47 of Bohr.
In reference to claim 13, Bohr in view of Park disclose a single second gate electrode, as addressed above in reference to claim 9. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the device to include a third gate electrode, the third gate electrode comprising: a fifth high-k dielectric layer that comprises the first material; a sixth high-k dielectric layer over and in contact with the fifth high-k dielectric layer, wherein the sixth high-k dielectric layer comprises the second material; and a fourth p-type work function tuning metal contacting the sixth high-k dielectric layer as a duplication of the second gate electrode. The courts have held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
In reference to claim 14, Bohr discloses a device comprising:
a first gate electrode, the first gate electrode comprising:
a dielectric layer 131 comprising a first material;
a first n-type work function tuning metal 161 contacting the third dielectric layer, paragraph 46;
a second p-type work function tuning metal 162 contacting the first n-type work function tuning metal, paragraph 47;
and a first conductive material 171 over the second p-type work function tuning metal, paragraph 48.
Bohr does not disclose a first dielectric layer comprising a first material;
a second dielectric layer over and in contact with the first dielectric layer, the second dielectric layer comprising a second material, wherein the second material is different from the first material;
a third dielectric layer over and in contact with the second dielectric layer, wherein the third dielectric layer comprises a third material that is different from the first material and the second material, and wherein a dielectric constant of the second dielectric layer and a dielectric constant of the third dielectric layer are higher than 3.9.
Park discloses an analogous device including teaching a first gate electrode comprising
a first dielectric layer, INL in Figure 3A, comprising a first material, paragraph 82;
a second dielectric layer HK1over and in contact with the first dielectric layer, the second dielectric layer comprising a second material, wherein the second material is different from the first material, paragraph 83;
a third dielectric layer HK2 over and in contact with the second dielectric layer, wherein the third dielectric layer comprises a third material that is different from the first material and the second material, paragraph 84 and wherein a dielectric constant of the second dielectric layer and a dielectric constant of the third dielectric layer are higher than 3.9, paragraph 48.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first gate electrode to comprise a first dielectric layer comprising a first material;
a second dielectric layer over and in contact with the first dielectric layer, the second dielectric layer comprising a second material, wherein the second material is different from the first material;
a third dielectric layer over and in contact with the second dielectric layer, wherein the third dielectric layer comprises a third material that is different from the first material and the second material, and wherein a dielectric constant of the second dielectric layer and a dielectric constant of the third dielectric layer are higher than 3.9.
One would have been motivated to do so in order to provide a thin gate dielectric with good reliability and a high breakdown voltage, paragraph 89.
In reference to claim 16, Park discloses the first dielectric layer comprises silicon oxide, paragraph 82.
In reference to claim 17, Park discloses a thickness of the second dielectric layer is greater than a thickness of the first dielectric layer and a thickness of the third dielectric layer, paragraph 95.
In reference to claim 18, Park discloses the thickness of the first dielectric layer is in a range from 0.7 nm to 2 nm, wherein the thickness of the second dielectric layer is in a range from 1 nm to 4 nm, and the thickness of the third dielectric layer is in a range from 1 nm to 2 nm, paragraph 95.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Park et al. (US 2023/0020176) as applied to claims 6 and 14 above and further in view of Lisiansky et al. (US 2009/0181530) and Agarwal (US 2001/0015453).
In reference to claims 7 and 15, Bohr in view of Park does not disclose the crystallinity of the first high-k dielectric layer and the second high-k dielectric layer is higher than 70 percent.
Lisiansky discloses an analogous semiconductor device including teaching a first high-k dielectric layer, 721 in Figure 7D, and a second high-k dielectric layer, 712, that are crystalline, paragraph 47, and Agarwal teaches high-k dielectric films considered to be crystalline when they have greater than or equal to about 70% crystallinity, paragraph 22.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the crystallinity of the first high-k dielectric layer and the second high-k dielectric layer to be higher than 70 percent. One would have been motivated to do so in order to provide a dielectric with low leakage current, paragraph 51.
Claims 11, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Park et al. (US 2023/0020176) as applied to claims 6 and 14 above and further in view of Li (US 2018/0151575).
In reference to claim 11, Bohr does not disclose the second p-type work function tuning metal and the third p-type work function tuning metal comprise titanium nitride, and the first n-type work function tuning metal comprises titanium aluminum nitride.
Li discloses an analogous semiconductor device including teaching a second p-type work function tuning metal and a third p-type work function tuning metal comprise titanium nitride, 320, 330 of transistors 11 and 21 in Figure 13, for example, paragraphs 77 and 94, and the first n-type work function tuning metal 400 comprises titanium aluminum nitride, paragraph 111.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second p-type work function tuning metal and the third p-type work function tuning metal to comprise titanium nitride, and the first n-type work function tuning metal to comprise titanium aluminum nitride.
One would have been motivated to do so in order to set a desired work function for the transistors, paragraphs 63 and 111.
In reference to claim 19, Bohr does not disclose the first n-type work function tuning metal comprises titanium aluminum nitride, and the second p-type work function tuning metal comprises titanium nitride.
Li discloses an analogous semiconductor device including teaching the first n-type work function tuning metal 400 comprises titanium aluminum nitride, paragraph 111, and a second p-type work function tuning metal comprise titanium nitride, 320, 330 of transistor 11 in Figure 13, for example, paragraphs 77 and 94.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first n-type work function tuning metal to comprise titanium aluminum nitride and the second p-type work function tuning metal to comprise titanium nitride.
One would have been motivated to do so in order to set a desired work function for the transistors, paragraphs 63 and 111.
In reference to claim 20, Bohr does not disclose the first n-type work function tuning metal comprises titanium aluminum carbide, and the second p-type work function tuning metal comprises titanium nitride.
Li discloses an analogous semiconductor device including teaching the first n-type work function tuning metal 400 comprises titanium aluminum carbide, paragraph 111, and a second p-type work function tuning metal comprise titanium nitride, 320, 330 of transistor 11 in Figure 13, for example, paragraphs 77 and 94.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first n-type work function tuning metal to comprise titanium aluminum carbide and the second p-type work function tuning metal to comprise titanium nitride.
One would have been motivated to do so in order to set a desired work function for the transistors, paragraphs 63 and 111.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bohr (US 2013/0267070) in view of Park et al. (US 2023/0020176) as applied to claim 10 above and further in view of Kelwing et al. (US 2013/0277766).
In reference to claim 12, Bohr in view of Park does not disclose the first high-k dielectric layer and the second high-k dielectric layer comprise hafnium oxide, zirconium oxide, or titanium oxide.
Kelwing et al. (US 2013/0277766) discloses an analogous semiconductor device including teaching a first high-k dielectric layer and a second high-k dielectric layer comprise hafnium oxide, zirconium oxide, or titanium oxide, paragraph 35. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first high-k dielectric layer and the second high-k dielectric layer to comprise hafnium oxide, zirconium oxide, or titanium oxide. One would have been motivated to do so in order to set a desire threshold voltage for the transistors, paragraphs 35-38.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chai et al. (US 2017/0256544), Lavric et al. (US 2019/0305102), Hoon (US 2014/0004693), Chiu et al. (US 2021/0407995), Choi et al. (US 2018/0151376), Lee et al. (US 2021/0233817), Savant et al. (US 2021/0074593) discloses related structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
Prosecution Insights