DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows:
Claims 1-20 are pending.
An action on the merits for claims 1-20 follows.
IDS
All references provided in the IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Memory Device Comprising Gate Local Interconnect Structure.
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract primarily tracts the structure of the claim, and thus the main focus and nature of the inventive concept and what is new is not readily apparent. Therefore, it may not be clear to a reader whether they need to consult the full patent text for details.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "NM1, NM2" and "NW1, NW2" have both been used to designate n-type wells in Figs. 6A and 7A appearing to correspond to the same regions. Additionally, NM1 and NM2 do not appear to be found in the specification. Similarly, characters "PW1" and "PW31" have both been used to designate a p-type well in Figs. 6A and 7A respectively. PW31 does not appear to be found in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because Fig. 6C (or the figure presumably intended to be Fig. 6C) contains an unreadable label, axes, and contains a plurality of labels that do not appear to be referenced in the specification. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Objections
Claim 11 is objected to because of the following claim term inconsistency: Claim 11 recites the limitation "the common source/drain feature.” There is insufficient antecedent basis for this limitation in the claim. It appears this limitation refers to “the common source/drain contact” referenced in claim 11 and will be interpreted as such for purposes of examination. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-8, 10-12, and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 20220384456 A1), hereinafter Liaw.
Regarding Claim 1, Liaw teaches a memory device ("SRAM array," (100); Figs. 15 (top-view), 16 (cross-sectional view), Paragraph [0049]; Note: "components […] depicted in Figs. 15-17 are consistent with those depicted in Figs. 3-7" and paragraphs referring to Figs. 3-7 may be used for citation purposes; Paragraph [0047]), comprising:
a first static random access memory (SRAM) cell ("SRAM cell," (101C); Fig. 15, Paragraph [0048]), wherein the first SRAM cell (101C) comprises:
a first active region ("p-type fin," (106-1); Annotated Fig. 15, Paragraph [0048]; Note: p/n -type fins are active regions as explained regarding an earlier embodiment Paragraph [0023]) and a second active region ("n-type fin," (108-2); Annotated Fig. 15, Paragraph [0048]), extending in a Y-direction ("Y-axis,," (Y-axis); Figs. 15, 16, Paragraph [0048]); and a
first gate structure ("gate stack," (130D); Fig. 15, Paragraph [0026]) and a second gate structure ("gate stack," (130C); Fig. 15, Paragraph [0026]), extending in an X-direction ("X-axis," (X-axis); Figs. 15, 16, Paragraph [0048]) that is perpendicular to the Y-direction (Y-axis), wherein the first gate structure (130D) is engaged with the first active region (106-1) to form a first pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), and wherein the second gate structure (130C) is engaged with the first active region (106-1) and the second active region (108-2) to form a first pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]) and a first pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), respectively;
a second SRAM cell ("SRAM cell," (101D); Fig. 15, Paragraph [0048]) adjacent to the first SRAM cell (101C) in the X-direction (X-axis), wherein the second SRAM cell (101D) shares a common boundary with the first SRAM cell (101C), and the second SRAM cell (101D) comprises:
a third active region ("p-type fin," (106-3); Annotated Fig. 15, Paragraph [0048]) and a fourth active region ("n-type fin," (108-4); Annotated Fig. 15, Paragraph [0048]), extending in the Y-direction (Y-axis); and
a third gate structure ("gate stack," (130D-2); Annotated Fig. 15, Paragraph [0026]) and a fourth gate structure ("gate stack," (130C-2); Annotated Fig. 15, Paragraph [0026]; Note: third and fourth gate structures are have similar structures to first and second gate structures in a different SRAM cell), extending in the X-direction (X-axis), wherein the third gate structure (130D-2) is engaged with the third active region (106-3) to form a second pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), and wherein the fourth gate structure (130C-2) is engaged with the third active region (106-3) and the fourth active region (108-4) to form a second pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]) and a second pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), respectively;
a first gate end dielectric layer ("dielectric fin," (160-1); Annotated Fig. 15, Paragraph [0048]), extending along the common boundary (a dotted line separates SRAM cells 101C and 101D; Fig. 15) that extends in the Y-direction (Y-axis), wherein the first gate end dielectric layer (160-1) is between the first gate structure (130D) and the third gate structure (130D-2), and separates the first gate structure (130D) from the third gate structure (130D-2); and
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a first gate local connection structure ("gate contact," (122-1); Annotated Fig. 15, Paragraph [0032]), extending in the X-direction (X-axis) and over the first gate structure (130D), the third gate structure (130D-2), and the first gate end dielectric layer (160), wherein the first gate local connection structure (122-1) electrically connects the first gate structure (130D) to the third gate structure (130D-2).
Regarding Claim 2, Liaw teaches the memory device of claim 1,
wherein each of the first SRAM cell (101C) and the second SRAM cell (101D) has a cell width ("long pitch," (Sx); Fig. 15, Paragraph [0022]) in the X-direction (X-axis) and a cell height ("short pitch," (Sy); Fig. 15, Paragraph [0022]) in the Y-direction (Y-axis), and
wherein the first gate end dielectric layer (160-1) continuously extends across the whole cell height (Sy; Fig. 15).
Regarding Claim 5, Liaw teaches the memory device of claim 1, wherein the first SRAM cell (101C) further comprises:
a fifth active region ("n-type fin," (108-5); Annotated Fig. 15, Paragraph [0048]) and a sixth active region ("p-type fin," (106-6); Annotated Fig. 15, Paragraph [0048]), extending in the Y-direction (Y-axis);
a fifth gate structure ("gate stack," (130B); Annotated Fig. 15, Paragraph [0026]) extending in the X-direction (X-axis), wherein the fifth gate structure (130B) is separated from the first gate structure (130D) in the X-direction and separated from the second gate structure (130C) in the Y-direction (Y-axis), and wherein the fifth gate structure (130B) is engaged with the fifth active region (108-5) and the sixth active region (108-6) to form a third pull-up transistor ("first pull-up transistor," (PU-1); Fig. 15, Paragraph [0026]) and a third pull-down transistor ("first pull-down transistor," (PD-1); Fig. 15, Paragraph [0026]), respectively; and
a sixth gate structure ("gate stack," (130A); Annotated Fig. 15, Paragraph [0026]) extending in the X-direction (X-axis), wherein the sixth gate structure (130A) is separated from the second gate structure (130C) in the X-direction (X-axis) and separated from the fifth gate structure (130B) in the Y-direction (Y-axis), and wherein the sixth gate structure (130A) is engaged with the sixth active region (106-6) to form a third pass-gate transistor ("first pass-gate transistor," (PG-1); Fig. 15, Paragraph [0026]).
Regarding Claim 6, Liaw teaches the memory device of claim 5, wherein the first SRAM cell (101C) further comprises:
a second gate end dielectric layer ("dielectric fin," (right 162); Fig. 15, Paragraph [0047]) between the first gate structure (130D) and the fifth gate structure (130B), wherein the second gate end dielectric layer (right 162) separates the first gate structure (130D) from the fifth gate structure (130B);
a third gate end dielectric layer ("dielectric fin," (left 162); Fig. 15, Paragraph [0047]) between the second gate structure (130C) and the sixth gate structure (130A), wherein the third gate end dielectric layer (left 162) separates the second gate structure (130C) from the sixth gate structure (130A); and
a fourth gate end dielectric layer ("dielectric fin," (160); Fig. 15, Paragraph [0047]), extending along a cell boundary that is opposite to the common boundary and extends in the Y-direction (Y-axis), wherein the fourth gate end dielectric layer (160) is in contact with the fifth gate structure (130B) and the sixth gate structure (130A).
Regarding Claim 7, Liaw teaches the memory device of claim 6, wherein the first SRAM cell (101C) further comprising:
a second gate local connection structure ("gate contact," (122); Fig. 15, Paragraph [0032]), over the sixth gate structure (130A) and the fourth gate end dielectric layer (160), wherein the second gate local connection structure (122) partially overlaps the sixth gate structure (130A).
Regarding Claim 8, Liaw teaches the memory device of claim 5,
wherein the first SRAM cell (101C) has a cell height ("short pitch," (Sy); Fig. 15, Paragraph [0022]) in the Y-direction (Y-axis),
wherein the second active region (108-2) and the fifth active region (108-5) continuously extend across the whole cell height (Sy),
wherein the fifth gate structure (130B) is engaged with the second active region (108-2) to form a first isolation transistor ("second isolation transistor," (IS-2); Fig. 15, Paragraph [0026])), and
wherein the second gate structure (130C) is engaged with the fifth active region (108-5) to form a second isolation transistor ("first isolation transistor," (IS-1); Fig. 15, Paragraph [0026]).
Regarding Claim 10, Liaw teaches a memory device ("SRAM array," (100); Figs. 15 (top-view), 16 (cross-sectional view), Paragraph [0049]; Note: "components […] depicted in Figs. 15-17 are consistent with those depicted in Figs. 3-7" and paragraphs referring to Figs. 3-7 may be used for citation purposes; Paragraph [0047]), comprising:
a first static random access memory (SRAM) cell ("SRAM cell," (101C); Fig. 15, Paragraph [0048]), comprising:
a first pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), a first pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]), a first pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), a second pass-gate transistor ("first pass-gate transistor," (PG-1); Fig. 15, Paragraph [0026]), a second pull-down transistor ("first pull-down transistor," (PD-1); Fig. 15, Paragraph [0026]), and a second pull-up transistor ("first pull-up transistor," (PU-1); Fig. 15, Paragraph [0026]),
wherein the first pass-gate transistor (PG-2) comprises a first gate structure ("gate stack," (130D); Fig. 15, Paragraph [0026]) and the first pull-down transistor (PD-2) and the first pull-up transistor (PU-2) share a second gate structure ("gate stack," (130C); Fig. 15, Paragraph [0026]),
wherein the first gate structure (130D) and the second gate structure (130C) extend in an X-direction ("X-axis,," (X-axis); Figs. 15, 16, Paragraph [0048]) and are separated from each other in a Y-direction ("Y-axis," (Y-axis); Figs. 15, 16, Paragraph [0048]) that is perpendicular to the X-direction (X-axis),
a second SRAM cell ("SRAM cell," (101D); Fig. 15, Paragraph [0048]) sharing a common boundary with the first SRAM cell (101C), wherein the common boundary extends in the Y-direction (Y-axis), wherein the second SRAM cell (101D)comprises: (As seen in Fig. 15, the first and second SRAM cells are comprised of the same types of transistors)
a third pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), a third pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]), a third pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), a fourth pass-gate transistor ("first pass-gate transistor," (PG-1); Fig. 15, Paragraph [0026]), a fourth pull-down transistor ("first pull-down transistor," (PD-1); Fig. 15, Paragraph [0026]), and a fourth pull-up transistor ("first pull-up transistor," (PU-1); Fig. 15, Paragraph [0026]),
wherein the third pass-gate transistor (PG-2) comprises a third gate structure ("gate stack," (130D-2); Annotated Fig. 15, Paragraph [0026]) and the third pull-down transistor (PD-2) and the third pull-up transistor (PU-2) share a fourth gate structure "gate stack," (130C-2); Annotated Fig. 15, Paragraph [0026]),
wherein the third gate structure (130D-2) and the fourth gate structure (130C-2) extend in the X-direction (X-axis), and are aligned with the first gate structure (130D) and the second gate structure (130C) along the X-direction (X-axis), respectively,
wherein the third gate structure (130D-2) is separated from the first gate structure (130D) in the X-direction (X-axis), and the fourth gate structure (130C-2) is separated from the second gate structure (130C) in the X-direction (X-axis), and
a first gate local connection structure ("gate contact," (122-1); Annotated Fig. 15, Paragraph [0032]), disposed on the first gate structure (130D) and the third gate structure (130D-2), wherein the first gate local connection structure (122-1) electrically connects the first gate structure (130D) to the third gate structure (130D-2).
Regarding Claim 11, Liaw teaches the memory device of claim 10, further comprising:
a common source/drain contact ("S/D contact," (120C); Fig. 15, Paragraph [0034]), electrically connected to a first source/drain feature ("S/D feature," (114N); Fig. 15, Paragraph [0034]) shared by the first pass-gate transistor (PG-2) and the first pull-down transistor (PD-2) and a second source/drain feature ("S/D feature," (114P); Fig. 15, Paragraph [0034]) of the first pull-up transistor (PU-2); and
a butted contact ("Butted contact" (124); Fig. 15, Paragraph [0032]), electrically connected to the common source/drain feature (assumed to be 120C, see previous claim objection) and a fifth gate structure ("gate stack," (130B); Annotated Fig. 15, Paragraph [0026]) shared by the second pull-up transistor (PU-1) and the second pull-down transistor (PD-1).
Regarding Claim 12, Liaw teaches the memory device of claim 10, further comprising:
a first gate end dielectric layer ("dielectric fin," (160-1); Annotated Fig. 15, Paragraph [0048]) extending along the common boundary,
wherein the first gate end dielectric layer (160-1) is between the first gate structure (130D) and the third gate structure (130D-2), and separates the first gate structure (130D) from the third gate structure (130D-2).
Regarding Claim 14, Liaw teaches the memory device of claim 12, wherein the first SRAM cell (101C) further comprises:
a second gate end dielectric layer ("dielectric fin," (160); Fig. 15, Paragraph [0047]), extending along a cell boundary that is opposite to the common boundary; and
a second gate local connection structure ("gate contact," (122); Fig. 15, Paragraph [0032]), disposed on the second gate end dielectric layer (160) and a sixth gate structure ("gate stack," (130A); Annotated Fig. 15, Paragraph [0026]) of the second pass-gate transistor (PG-1), wherein the second gate local connection structure (122) partially overlaps the sixth gate structure (130A; Fig. 15).
Regarding Claim 15, Liaw teaches the memory device of claim 14, wherein the first SRAM cell has a cell height ("short pitch," (Sy); Fig. 15, Paragraph [0022]) in the Y-direction (Y-axis), and wherein the first gate end dielectric layer (160-1) and the second gate end dielectric layer (160) continuously extend across the whole cell height (Sy).
Regarding Claim 16, Liaw teaches a memory device ("SRAM array," (100); Figs. 15 (top-view), 16-17 (cross-sectional views), Paragraph [0049]; Note: "components […] depicted in Figs. 15-17 are consistent with those depicted in Figs. 3-7" and paragraphs referring to Figs. 3-7 may be used for citation purposes; Paragraph [0047]), comprising:
a first static random access memory (SRAM) cell ("SRAM cell," (101C); Fig. 15, Paragraph [0048]) over a substrate ("substrate," (12); Fig. 16, Paragraph [0027]), comprising:
a first pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), comprising first nanostructures ("stack of semiconductor layers," (105) that are "wrapped around by" 130D; Fig. 16, Paragraph [0028]) that are vertically stacked and wrapped around by a first gate structure ("gate stack," (130D); Fig. 15, Paragraph [0026]);
a first pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]), comprising second nanostructures ("stack of semiconductor layers," (105) that are "wrapped around by" 130C; Fig. 16, Paragraph [0028])) that are vertically stacked and wrapped around by a second gate structure ("gate stack," (130C); Fig. 15, Paragraph [0026]); and
a first pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), comprising third nanostructures ("stack of semiconductor layers," (107) that are "wrapped around by" 130C; Fig. 16, Paragraph [0028])) that are vertically stacked and wrapped around by the second gate structure (130C),
wherein the first gate structure (130D) and the second gate structure (130C) extend in an X-direction ("X-axis," (X-axis); Figs. 15, 16, Paragraph [0048]) and are separated from each other in a Y-direction ("Y-axis,," (Y-axis); Figs. 15, 16, Paragraph [0048]) that is perpendicular to the X-direction (X-axis),
a second SRAM cell ("SRAM cell," (101D); Fig. 15, Paragraph [0048]) over the substrate (12) and adjacent to the first SRAM cell (101C), comprising:
a second pass-gate transistor ("second pass-gate transistor," (PG-2); Fig. 15, Paragraph [0026]), comprising fourth nanostructures ("stack of semiconductor layers," (105) that are "wrapped around by" 130D-2; Fig. 16, Paragraph [0028])) that are vertically stacked and wrapped around by a third gate structure ("gate stack," (130D-2); Annotated Fig. 15, Paragraph [0026]);
a second pull-down transistor ("second pull-down transistor," (PD-2); Fig. 15, Paragraph [0026]), comprising fifth nanostructures ("stack of semiconductor layers," (105) that are "wrapped around by" 130C-2; Fig. 16, Paragraph [0028])) that are vertically stacked and wrapped around by a fourth gate structure ("gate stack," (130C-2); Annotated Fig. 15, Paragraph [0026]); and
a second pull-up transistor ("second pull-up transistor," (PU-2); Fig. 15, Paragraph [0026]), comprising sixth nanostructures ("stack of semiconductor layers," (107) that are "wrapped around by" 130C-2; Fig. 16, Paragraph [0028])) that are vertically stacked and wrapped around by the fourth gate structure (130C-2),
wherein the third gate structure (130D-2) and the fourth gate (130C-2) structure are aligned with the first gate structure (130D) and the second gate structure (130C) along the X-direction (X-axis), respectively,
a first gate end dielectric layer ("dielectric fin," (160-1); Annotated Fig. 15, Paragraph [0048]), disposed between the first SRAM cell (101C) and the second SRAM cell (101D) and extending the Y-direction (Y-axis), wherein the first gate end dielectric layer (160-1) physically separates the first gate structure (130D) from the third gate structure (130D-2) and physically separates the second gate structure (130C) from the fourth gate structure (130C-2; Fig. 15); and
a first gate local connection structure ("gate contact," (122-1); Annotated Fig. 15, Paragraph [0032]), disposed on the first gate structure (130D), the third gate structure (130D-2), and the first gate end dielectric layer (160-1), wherein the first gate local connection structure (122-1) electrically connects the first gate structure (130D) to the third gate structure (130D-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Liaw (US 20220278110 A1), hereinafter Liaw110.
Regarding Claim 3, Liaw teaches the memory device of claim 2.
Liaw does not explicitly teach wherein a ratio of the cell width to the cell height is in a range from 1.5 to 3.
Liaw110 teaches at least a memory device (“HD SRAM cell,” (104); Fig. 2, Paragraph [0042]; Note: Paragraphs [0025, 0042]) wherein a ratio of the cell width (“length,” (X1); Fig. 2, Paragraph [0025]) to the cell height (“width,” (Y1); Fig. 2, Paragraph [0025]) is in a range from 1.5 to 3 (“a ratio of X1 to Y1 may be […] in a range of 2 to 2.5;” Paragraph [0042]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the range of Liaw110. Implementing an SRAM cell of this size ratio has the added benefit of being disposed in a thin slice which simplifies the layout of the memory device (Paragraph [0042]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Wang et al. (US 20210265202 A1), hereinafter Wang.
Regarding Claim 4, Liaw teaches the memory device of claim 1, wherein the first gate local connection structure (122-1) partially overlaps each of the first gate structure (130D) and the third gate structure (130D-2) by a distance.
Liaw does not explicitly teach wherein the distance is in a range from 3 nm to 20 nm.
Wang teaches at least a memory device (“semiconductor device may, for example, be […] a memory cell,” (124); Fig. 1A, Paragraph [0030]) wherein the first gate local connection structure (“gate via,” (114); Fig. 1A, Paragraph [0028]) partially overlaps (by width, (Wgv); Fig. 1A) the first gate structure (“gate electrode,” (104); Fig. 1A, Paragraph [0028]) by a distance that is in a range from 3 nm to 20 nm (“about 8.0-16.5 nanometers;” Paragraph [0028]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Wang such that the gate local connection structure overlaps each of the first gate structure and the third gate structure by a distance that is in a range from 3nm to 20nm. This is because, having a suitable overlap between the local connection structure and gate structure prevents seams and voids and prevents the connection structure from being too close to other contacts which would lead to leakage current (Paragraph [0028]). Applying this overlap to both the first and third gate structures in accordance with the existing purpose of Liaw prevents being too close to another contact on both sides of the local connection structure.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Liaw (US 20220328499 A1), hereinafter Liaw499.
Regarding Claim 9, Liaw teaches the memory device of claim 1, wherein the first SRAM cell (101C) further comprises:
a via (“via,” (126B); Fig. 7B, Paragraph [0036]); and
a word line (“word line,” (WL); FFig. 7B, Paragraph [0036]), disposed on the via (126B) and extending in the X-direction (X-axis), wherein the word line (WL) is electrically connected to the first gate structure (130D) and the third gate structure (130D-2; not shown in Fig.7B but is connected to 130D of the first SRAM cell) through the via (126B), and the first gate local connection structure (122).
Liaw does not explicitly teach wherein the first SRAM cell further comprises:
a word line landing pad, disposed on the first gate local connection structure;
wherein a via is disposed on the word line landing pad; and
wherein the word line is electrically connected to the first gate structure and the third gate structure through the word line landing pad.
Liaw499 teaches at least a memory device (“semiconductor device,” (200) Figs. 1A (simplified diagram), 3 (portion of memory array of Fig. 1A), 11 (cross-section of Fig. 3), Paragraph [0023]), wherein a first SRAM cell (“SRAM cell,” (104); Fig. 1A, Paragraph [0023]) further comprises:
a word line landing pad (“word line landing pad [is] located at a first metal layer,” (M1); Fig. 11, Paragraph [0068]) disposed on the first gate local connection structure (“gate via,” (gate via); Fig 11, Paragraph [0068]);
wherein a via (“level-1 via,” (via1); Fig. 11, Paragraph [0041]) is disposed on the word line landing pad (M1); and
wherein the word line (M1) is electrically connected to the first gate structure (“Gate;” Fig. 11) and the third gate structure (“Gate;” Fig. 11) through the word line landing pad (M1). (“two adjacent TP SRAM cells shares a common […] common write word line (W_WL) landing pad at the M1 layer” connecting both gate structures to the word line landing pad through the gate via)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Liaw499 such that the device includes a word line landing pad. This is because including a word line landing pad provides a shared landing area for the gate electrodes connecting to conductive lines at higher levels of the device, reducing needed space by sharing between adjacent cells (Paragraph [0021].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Radlinger eta l. (US 20230197826 A1), hereinafter Radlinger.
Regarding Claim 13, Liaw teaches the memory device of claim 12.
Liaw does not explicitly teach wherein top surfaces of the first gate structure, the third gate structure, and the first gate end dielectric layer are coplanar with a bottom surface of the first gate local connection structure.
Radlinger teaches an analogous device (“integrated circuit structure,” ( 730); Fig. 7B, Paragraph [0080]) wherein top surfaces of the first gate structure (left “gate stack,” (left 108); Paragraph [0080]), the third gate structure (right “gate stack,” (right 108); Paragraph [0080]), and the first gate end dielectric layer (“dielectric wall,” (734); Paragraph [0080]) are coplanar with a bottom surface of the first gate local connection structure (“local conductive interconnect,” (736); Fig. 2B, Paragraph [0080]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Radlinger such that the top surfaces of the first gate structure, the third gate structure, and the first gate end dielectric layer are coplanar with a bottom surface of the first gate local connection structure. This is because the coplanar structure allows the local interconnect to electrically connect completely separated gate electrodes across the intervening dielectric layer and allows for ease of forming the local interconnect (Paragraph [0080]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Chu et al. (US 20220359066 A1), hereinafter Chu.
Regarding Claim 17, Liaw teaches the memory device of claim 16, further comprising:
a shallow trench isolation (STI) structure (“isolation structures […] include STI features,” (14); Fig. 16, Paragraph [0027]) below the first gate structure (130D; corresponding to left PG-2 as per Fig. 15) and the third gate structure (130D-2; corresponding to right PG-2 as per Fig. 15),
wherein the first gate end dielectric layer (160) extends into the STI structure (14) by a distance (Fig. 16).
Liaw does not explicitly teach wherein the first gate end dielectric layer extends into the STI structure by a distance that is in a range from 5 nm to 60 nm.
Chu teaches at least a memory device (“semiconductor device;” Fig. 17D, Paragraph [0006]) showing an analogous structure of gate stacks separated by dielectrics wherein the first gate end dielectric layer (“first ILD,” (96); Fig. 17D, Paragraph [0057]) extends into the STI structure (“STI regions […] have a second rounded profile,” (58); Fig. 17D, Paragraph [0057]) by a distance that is in a range from 5 nm to 60 nm (“second rounded profile in the shallow trench isolation region to a depth below the top surface of the shallow trench isolation region from 5 nm to 25 nm;” Paragraph [0060]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Chu such that the first gate end dielectric layer extends into the STI structure by a distance that is in a range from 5 nm to 60 nm. Extending the dielectric structure into the STI structure by this amount minimizes material loss from the STI region by not completely piercing the STI structure, improving the resistance of the STI structure, and improved device efficiency (Paragraph [0057]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Xie et al. (US 20200365687 A1), hereinafter Xie.
Regarding Claim 18, Liaw teaches the memory device of claim 16,
wherein the first pass-gate transistor (PG-2) comprises a first source/drain feature ("S/D feature" above 130D, (114N); Annotated Fig. 15, Paragraph [0034]) and a second source/drain feature ("S/D feature" between 130D and 130C (114N); Annotated Fig. 15, Paragraph [0034]) disposed on opposite sides of the first gate structure (130D),
wherein the first pull-down transistor (PD-2) comprises the second source/drain feature (114N, between 130D and 130C) and a third source/drain feature ("S/D feature," below 130C, (114N); Annotated Fig. 15, Paragraph [0034]) disposed on opposite sides of the second gate structure (130C).
Liaw does not explicitly teach wherein the first SRAM cell further comprises bottom isolation layers disposed between the substrate and each of the first source/drain feature, the second source/drain feature, and the third source/drain feature.
Xie teaches an analogous structure (“semiconductor structure,” (100); Figs. 1, 7 (cross-sectional view of Fig. 1, Paragraph [0058]) that further comprises bottom isolation layers (“semiconductor buffer layer,” (702); Fig. 7, Paragraph [0058]) disposed between the substrate (“substrate,” (204); Paragraph [0036]) and each of the first source/drain feature, the second source/drain feature, and the third source/drain feature (collectively “source and drain regions,” (704); Fig. 7, Paragraph [0059]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Xie to include bottom isolation layers between the substrate and source/drain features. Xie teaches forming a bottom isolation layer between each source/drain feature and the substrate (Paragraph [0058]) which has the benefit of more easily epitaxially growing the source/drain feature from the surface as opposed to the sidewall of nanostructures, resulting in a much faster process (Paragraph [0059]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Wang and Radlinger.
Regarding Claim 19, Liaw teaches the memory device of claim 16,
wherein the first gate local connection structure (122-1) partially overlaps each of the first gate structure (130D) and the third gate structure (130D-2) by a range in the X-direction (X-axis).
Liaw does not explicitly teach wherein top surfaces of the first gate structure, the third gate structure, and the first gate end dielectric layer are coplanar with a bottom surface of the first gate local connection structure, and
wherein the range is from 3 nm to 20 nm.
Wang teaches at least a memory device (“semiconductor device may, for example, be […] a memory cell,” (124); Fig. 1A, Paragraph [0030]) wherein the first gate local connection structure (“gate via,” (114); Fig. 1A, Paragraph [0028]) partially overlaps (by width, (Wgv); Fig. 1A) the first gate structure (“gate electrode,” (104); Fig. 1A, Paragraph [0028]) by a distance that is in a range from 3 nm to 20 nm (“about 8.0-16.5 nanometers;” Paragraph [0028]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Wang such that the gate local connection structure overlaps each of the first gate structure and the third gate structure by a distance that is in a range from 3nm to 20nm. This is because, having a suitable overlap between the local connection structure and gate structure prevents seams and voids and prevents the connection structure from being too close to other contacts which would lead to leakage current (Paragraph [0028]) Applying this overlap to both the first and third gate structures in accordance with the existing purpose of Liaw prevents being too close to another contact on both sides of the local connection structure.
Liaw as modified by Wang does not explicitly teach wherein top surfaces of the first gate structure, the third gate structure, and the first gate end dielectric layer are coplanar with a bottom surface of the first gate local connection structure.
Radlinger teaches an analogous device (“integrated circuit structure,” ( 730); Fig. 7B, Paragraph [0080]) wherein top surfaces of the first gate structure (left “gate stack,” (left 108); Paragraph [0080]), the third gate structure (right “gate stack,” (right 108); Paragraph [0080]), and the first gate end dielectric layer (“dielectric wall,” (734); Paragraph [0080]) are coplanar with a bottom surface of the first gate local connection structure (“local conductive interconnect,” (736); Fig. 2B, Paragraph [0080]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Radlinger such that the top surfaces of the first gate structure, the third gate structure, and the first gate end dielectric layer are coplanar with a bottom surface of the first gate local connection structure. This is because the coplanar structure allows the local interconnect to electrically connect completely separated gate electrodes across the intervening dielectric layer and allows for ease of forming the local interconnect (Paragraph [0080]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Chen et al. (US 20190371933 A1), hereinafter Chen and Huang, (US 20220310603 A1), hereinafter Huang.
Regarding Claim 20, Liaw teaches the memory device of claim 16,
wherein the first gate local connection structure (122-1) has a length in the X-direction (X-axis) and a width in the Y-direction (Y-axis), and
wherein the first gate local connection structure (122-1) has a thickness in a Z-direction (“Z-axis,” (Z-axis); Paragraph [0028]) that is perpendicular to the X-direction (X-axis) and the Y-direction (Y-axis).
Liaw does not explicitly teach wherein a ratio of the length to the width is in a range from 3 to 10, and wherein the thickness is in a range from 3 nm to 30 nm.
Chen teaches at least a memory device (“semiconductor structure;” Fig. 12A, Paragraph [0004]) wherein the first gate local connection structure (“local interconnection feature,” (230); Fig. 12A, Paragraph [0050]) has a length in the X-direction and a width in the Y-direction, and wherein a ratio of the length to the width is in a range from 3 to 10 (“length to width ratio greater than 2;” Paragraph [0050]: this range substantially overlaps the claimed non-critical range).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Chen such that the first gate local connection structure has a ratio of length to width between 3 and 10. It would be obvious to implement this shape of the first gate local connection structure in the claimed range as it is beneficial for providing an electrical connection between two contacts over a dielectric and ensuring an elongated shape (Paragraphs [0048, 0050]).
Liaw as modified by Chen does not explicitly teach wherein the thickness is in a range from 3 nm to 30 nm.
Huang teaches at least a memory device (“semiconductor device,” (100); Fig. 20F, Paragraph [0074]) wherein the first gate local connection structure (“gate via contact,” (335b); Fig. 20F, Paragraph [0074]) has a thickness in a Z-direction (vertical direction; Fig. 20F) that is perpendicular to the X-direction (lateral direction; Fig. 20F) and the Y-direction (into the page direction; Fig. 20F), and wherein the thickness is in a range from 3 nm to 30 nm (“has a height in a range of about 10nm to about 50nm;” Paragraph [0074]: this range substantially overlaps the non-critical claimed range ).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention disclosed by Liaw with the teachings of Huang to be within the specified, substantially overlapping, claimed range of a thickness of the gate local connection structure. The thickness of the gate via can be modified for the purpose of connecting a gate to a conductive line through a dielectric layer (Paragraph [0070]) and it would be obvious to optimize this thickness based on the thickness of the dielectric separating the conductive element and the gate.
Conclusion
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/NOLAN GABRIEL STUESSY/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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