DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2025 and 10/22/2025 are being considered by the examiner.
Drawings
The drawings submitted on 05/16/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kang et al. (US 20210098592 A1).
Regarding claim 1, Kang discloses a semiconductor device, comprising:
a stacking structure (160) disposed on a semiconductor substrate (101/105); ([0023], Fig. 2A)
a first sidewall spacer (161) and a second sidewall spacer (162) covering a sidewall of the stacking structure (160), wherein an air gap (169) is sealed between the first and second sidewall spacers (161/162), wherein topmost ends of the first sidewall spacer (161), the air gap (169), and the second sidewall spacer (162) and a top surface of the stacking structure (160) are coplanar, and a top portion of the air gap (169) is tapered toward the topmost end of the air gap (169); and
a contact plug (185) disposed between a pair of the stacking structures (160). (Fig. 2A)
Regarding claim 2, Kang discloses the semiconductor device of claim 1, wherein the air gap (169) is substantially identical to the first and second sidewall spacers (161/162) in terms of shape. (Fig. 2A)
Regarding claim 3, Kang discloses the semiconductor device of claim 1, wherein the air gap (169) laterally spans from an outer sidewall of the first sidewall spacer (161) to an inner sidewall of the second sidewall spacer (162). (Fig. 2A)
Regarding claim 4, Kang discloses the semiconductor device of claim 1, wherein the first sidewall spacer (161) and the second sidewall spacer (162) are respectively formed of a carbon-containing material. ([0036], Fig. 2A)
Regarding claim 5, Kang discloses the semiconductor device of claim 4, wherein the carbon-containing material comprises high-density carbon (HDC), silicon carbide or silicon carbonitride. ([0036], Fig. 2A)
Regarding claim 6, Kang discloses the semiconductor device of claim 1, wherein the stacking structure (160) comprises:
a gate electrode (165) disposed over the semiconductor substrate (101); ([0030, Fig. 2A) and
a gate dielectric layer (164) disposed between the gate electrode (165) and the semiconductor substrate (101). ([0030, Fig. 2A)
Regarding claim 7, Kang discloses the semiconductor device of claim 6, wherein the stacking structure (160) further comprises a hard mask (166) disposed on the gate electrode (165). ([0030, Fig. 2A)
Regarding claim 8, Kang discloses the semiconductor device of claim 6, further comprising: source/drain structures (150) disposed in the semiconductor substrate (101/105); ([0028], Fig. 2A) and
contact plugs (185) respectively standing on one of the source/drain structures (150) and electrically connected to the source/drain structures (150). ([0045, Fig. 2A)
Regarding claim 9, Kang discloses the semiconductor device of claim 8, wherein the contact plugs (185) are laterally spaced apart from the stacking structure (160) by the first sidewall spacer (161), the second sidewall spacer (162) and the air gap (169). (Fig. 2A)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20210098592 A1) as applied to claim 9 above, and further in view of Lee et al. (US 20230307370 A1).
Regarding claim 10, Kang discloses the semiconductor device of claim 9. Kang does not disclose wherein each of the contact plugs comprises: a conductive structure; a second barrier layer disposed on the conductive structure; and a top conductive layer disposed on the second barrier layer.
However, Lee discloses:
wherein each of the contact plugs (140) comprises:
a conductive structure (140_2); (Fig. 1)
a second barrier layer (180_1) disposed on the conductive structure (140_2); (Fig. 1) and
a top conductive layer (180_2) disposed on the second barrier layer (180_1). (Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Lee for each of the contact plugs comprises: a conductive structure; a second barrier layer disposed on the conductive structure; and a top conductive layer disposed on the second barrier layer in order to have “ high integration and low power consumption” (Lee, [0003])
Regarding claim 14, Lee discloses the semiconductor device of claim 10, wherein the second barrier layer (180_1) comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. ([0048, Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for similar reasons mentioned beforehand.
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for the second barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 15, Lee discloses the semiconductor device of claim 10, wherein the top conductive layer (180_2) comprises aluminum, tungsten, copper, or a combination thereof. ([0049, Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for the top conductive layer comprises aluminum, tungsten, copper, or a combination thereof since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230307370 A1) as applied to claim 10 above, and further in view of Murakami (US 20180286673 A1).
Regarding claim 11, Lee discloses the semiconductor device of claim 10. Lee does not disclose wherein the conductive structure comprises: a conductive concave layer disposed over the substrate and comprising a top surface having a V-shaped cross-sectional profile; and a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate.
However, Murakami discloses:
wherein the conductive structure comprises:
a conductive concave layer (204) disposed over the substrate (200) and comprising a top surface having a V-shaped cross-sectional profile; (Fig. 2E) and
a conductive filling layer (205) disposed on the conductive concave layer (204), wherein a surface of the conductive filling layer (205) is concave with respect to the substrate (200). ([0037], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for the conductive structure comprises: a conductive concave layer disposed over the substrate and comprising a top surface having a V-shaped cross-sectional profile; and a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate in order to “suppress generation of voids.” (Murakami, [0009])
Regarding claim 12, Murakami discloses the semiconductor device of claim 11, wherein the conductive filling layer (205) comprises germanium or silicon germanium. ([0037], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for similar reasons mentioned beforehand.
Regarding claim 13, Murakami discloses the semiconductor device of claim 12, wherein the conductive concave layer (204) comprises silicon and/or germanium with substantially no oxygen and no nitrogen. ([0031], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for similar reasons mentioned beforehand.
Conclusion
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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