DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/26/2026 was filed after the mailing date of the Non-Final Rejection on 06/17/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicants’ arguments, see pages 5-11 , filed 08/01/2026, with respect to the rejection(s) of claims 1-9 under 102 and claims 10-15 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Huang (US 20220254899 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-9, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20210098592 A1) in view of Huang (US 20220254899 A1).
Regarding claim 1, Kang discloses a semiconductor device, comprising:
a stacking structure (160) disposed on a semiconductor substrate (101/105); ([0023], Fig. 2A)
a first sidewall spacer (161) and a second sidewall spacer (162) covering a sidewall of the stacking structure (160), wherein an air gap (169) is formed between the first and second sidewall spacers (161/162), wherein topmost ends of the first sidewall spacer (161), the air gap (169), and the second sidewall spacer (162) and a top surface of the stacking structure (160) are coplanar, and a top portion of the air gap (169) is tapered toward the topmost end of the air gap (169); and
a contact plug (185) disposed between a pair of the stacking structures (160). (Fig. 2A)
Kang does not disclose:
wherein the topmost end of the air gap is an opened end between the topmost end of the first sidewall spacer and the topmost end of the second sidewall spacer.
However, Huang discloses
wherein the topmost end of the air gap (AG) is an opened end between the topmost end of the first sidewall spacer (110a) and the topmost end of the second sidewall spacer (110b). ([0024], Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Huang for wherein the topmost end of the air gap is an opened end between the topmost end of the first sidewall spacer and the topmost end of the second sidewall spacer so that “a parasitic capacitance between the gate electrode and a possible conductive component (e.g., a contact plug) aside the gate electrode can be reduced. Accordingly, RC delay on signal transmission through the gate electrode and the possible electrical component aside the gate electrode can be effectively minimized.” (Huang, [0062])
Regarding claim 2, Kang discloses the semiconductor device of claim 1, wherein the air gap (169) is substantially identical to the first and second sidewall spacers (161/162) in terms of shape. (Fig. 2A)
Regarding claim 3, Kang discloses the semiconductor device of claim 1, wherein the air gap (169) laterally spans from an outer sidewall of the first sidewall spacer (161) to an inner sidewall of the second sidewall spacer (162). (Fig. 2A)
Regarding claim 4, Kang discloses the semiconductor device of claim 1, wherein the first sidewall spacer (161) and the second sidewall spacer (162) are respectively formed of a carbon-containing material. ([0036], Fig. 2A)
Regarding claim 5, Kang discloses the semiconductor device of claim 4, wherein the carbon-containing material comprises high-density carbon (HDC), silicon carbide or silicon carbonitride. ([0036], Fig. 2A)
Regarding claim 6, Kang discloses the semiconductor device of claim 1, wherein the stacking structure (160) comprises:
a gate electrode (165) disposed over the semiconductor substrate (101); ([0030, Fig. 2A) and
a gate dielectric layer (164) disposed between the gate electrode (165) and the semiconductor substrate (101). ([0030, Fig. 2A)
Regarding claim 7, Kang discloses the semiconductor device of claim 6, wherein the stacking structure (160) further comprises a hard mask (166) disposed on the gate electrode (165). ([0030, Fig. 2A)
Kang does not disclose:
wherein the topmost end of the first sidewall spacer, the topmost end of the air gap, the topmost end of the second sidewall spacer, and a top surface of the hard mask are coplanar.
However, Huang discloses:
wherein the topmost end of the first sidewall spacer (110a), the topmost end of the air gap (AG), the topmost end of the second sidewall spacer (110b), and a top surface of the hard mask (108) are coplanar. ([0021], Fig. 1)
It would have been obvious to use the teachings of Huang for similar reasons mentioned beforehand.
Regarding claim 8, Kang discloses the semiconductor device of claim 6, further comprising: source/drain structures (150) disposed in the semiconductor substrate (101/105); ([0028], Fig. 2A) and
contact plugs (185) respectively standing on one of the source/drain structures (150) and electrically connected to the source/drain structures (150). ([0045, Fig. 2A)
Regarding claim 9, Kang discloses the semiconductor device of claim 8, wherein the contact plugs (185) are laterally spaced apart from the stacking structure (160) by the first sidewall spacer (161), the second sidewall spacer (162) and the air gap (169). (Fig. 2A)
Regarding claim 16, Huang discloses the semiconductor device of claim 1, further comprising:
a first dielectric layer (114) disposed on the semiconductor substrate (100) to surround the stacking structure (102); ([0027], Fig. 1) and
a second dielectric layer (116) disposed on a top surface of the first dielectric layer (114), wherein the topmost end of the air gap (AG) is sealed by the second dielectric layer (116). (Fig. 1)
It would have been obvious to use the teachings of Huang for similar reasons mentioned beforehand.
Regarding claim 17, Huang discloses the semiconductor device of claim 16, wherein the topmost end of the first sidewall spacer (110a), the topmost end of the air gap (AG), the topmost end of the second sidewall spacer (110b), and the top surface of the first dielectric layer (114) are coplanar. ([0027], Fig. 1)
It would have been obvious to use the teachings of Huang for similar reasons mentioned beforehand.
Claims 10, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 20210098592 A1) as applied to claim 9 above, and further in view of Lee et al. (US 20230307370 A1).
Regarding claim 10, Kang discloses the semiconductor device of claim 9. Kang does not disclose wherein each of the contact plugs comprises: a conductive structure; a second barrier layer disposed on the conductive structure; and a top conductive layer disposed on the second barrier layer.
However, Lee discloses:
wherein each of the contact plugs (140) comprises:
a conductive structure (140_2); (Fig. 1)
a second barrier layer (180_1) disposed on the conductive structure (140_2); (Fig. 1) and
a top conductive layer (180_2) disposed on the second barrier layer (180_1). (Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kang and Lee for each of the contact plugs comprises: a conductive structure; a second barrier layer disposed on the conductive structure; and a top conductive layer disposed on the second barrier layer in order to have “ high integration and low power consumption” (Lee, [0003])
Regarding claim 14, Lee discloses the semiconductor device of claim 10, wherein the second barrier layer (180_1) comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. ([0048, Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for similar reasons mentioned beforehand.
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for the second barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 15, Lee discloses the semiconductor device of claim 10, wherein the top conductive layer (180_2) comprises aluminum, tungsten, copper, or a combination thereof. ([0049, Fig. 1)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for the top conductive layer comprises aluminum, tungsten, copper, or a combination thereof since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230307370 A1) as applied to claim 10 above, and further in view of Murakami (US 20180286673 A1).
Regarding claim 11, Lee discloses the semiconductor device of claim 10. Lee does not disclose wherein the conductive structure comprises: a conductive concave layer disposed over the substrate and comprising a top surface having a V-shaped cross-sectional profile; and a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate.
However, Murakami discloses:
wherein the conductive structure comprises:
a conductive concave layer (204) disposed over the substrate (200) and comprising a top surface having a V-shaped cross-sectional profile; (Fig. 2E) and
a conductive filling layer (205) disposed on the conductive concave layer (204), wherein a surface of the conductive filling layer (205) is concave with respect to the substrate (200). ([0037], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for the conductive structure comprises: a conductive concave layer disposed over the substrate and comprising a top surface having a V-shaped cross-sectional profile; and a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate in order to “suppress generation of voids.” (Murakami, [0009])
Regarding claim 12, Murakami discloses the semiconductor device of claim 11, wherein the conductive filling layer (205) comprises germanium or silicon germanium. ([0037], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for similar reasons mentioned beforehand.
Regarding claim 13, Murakami discloses the semiconductor device of claim 12, wherein the conductive concave layer (204) comprises silicon and/or germanium with substantially no oxygen and no nitrogen. ([0031], Fig. 2E)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee in view of Murakami for similar reasons mentioned beforehand.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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