Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-13 are pending and examined below.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 07/16/2025 ("07-16-25 IDS") and 10/15/2025 (“10-15-25 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 07-16-25 IDS and 10-15-25 IDS are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING TESTING MODULE DISPOSED WITHIN SCRIBE LINE AND METHOD FOR MANUFACTURING THE SAME
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 is indefinite, because “the first testing pad” lacks antecedent basis. For the purpose of advancing the examination of the instant application, "the first testing pad" has been assumed to refer to "a testing pad."
Claim 5 is indefinite for the same reason that claim 4 is indefinite.
Claim 6 is indefinite, because it depends from the indefinite claim 4.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2014/0319522 A1 to Daubenspeck et al. ("Daubenspeck").
Figs. 4 and 5 of Daubenspeck have been annotated to support the rejection
below:
[AltContent: textbox (CR)][AltContent: arrow][AltContent: connector][AltContent: textbox (TM3 (TP3))][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (AR2)][AltContent: arrow][AltContent: textbox (AR1)][AltContent: arrow][AltContent: textbox (TM2 (TP2))][AltContent: textbox (TM1 (TP1))][AltContent: textbox (D1)][AltContent: textbox (D2)][AltContent: arrow][AltContent: arrow]
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[AltContent: textbox (TP)][AltContent: arrow][AltContent: textbox (TM1)][AltContent: arrow][AltContent: rect][AltContent: textbox (V1)][AltContent: arrow]
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382
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Regarding independent claim 1, Daubenspeck teaches a semiconductor device (see Fig. 5, for example), comprising:
a first active region AR1 (Fig. 4 shows four active regions 210. One of the four active regions has been annotated as AR1.) and a second active region AR2 separated by the first active region AR1 by a scribe line 220 (para [0049] - “kerf region 220”), wherein the scribe line 220 extends along a first direction D1; and
a first testing module TM1 (para [0050] - “one or more testing structures 221 for performing wafer-level testing of the integrated circuit chip…However, it should be understood that the devices 211 can comprise any number of suitable integrated circuit devices (e.g., planar field effect transistors, non-planar field effect transistors, bipolar transistors, capacitors, diodes, etc.), according to the design of the integrated circuit chip. Similarly, the test structures 221 can comprise any number of suitable test devices (e.g., planar field effect transistors, non-planar field effect transistors, bipolar transistors, capacitors, diodes, etc.) or parametric measurement macros suitable for wafer-level testing of the integrated circuit chips, as designed.”) abutting the first active region AR1 and disposed within the scribe line 220, wherein the first testing module TM1 comprises:
a testing pad TP (para [0052] - “additional metal interconnect(s) 217 can also be formed within the stack 202. Each additional metal interconnect 217 comprise, for example, an additional combination of metal wires and vias that extend from a test structure 221 in a kerf region 220 of the semiconductor layer 201 to the top surface 203 of the stack 202.”);
a testing circuit 221; and
a via structure V1 connecting the testing pad TP and the testing circuit 221, wherein the via structure V1 is closer to the first active region AR1 than the first testing circuit 221 is.
Regarding claim 2, Daubenspeck teaches a second testing module TM2 abutting the second active region AR2 and disposed within the scribe line 220, wherein the first testing module TM1 and the second testing module TM2 are arranged along a second direction D2 substantially orthogonal to the first direction D1.
Regarding claim 3, Daubenspeck teaches the second testing module TM2 that comprises a second testing pad TP2 (217) and a second testing circuit 221 along the second direction D2.
Regarding claim 4, Daubenspeck teaches the second testing pad TP2 (217) that is aligned with the first testing pad TP1 along the second direction D2.
Regarding claim 5, Daubenspeck teaches the second testing pad TP2 that is misaligned with the first testing pad TP1 along the second direction D2.
Regarding claim 6, Daubenspeck teaches the second testing pad TP2 that is (partially) aligned with the first testing pad TP1 along the second direction D2.
Regarding claim 7, Daubenspeck teaches the scribe line 220 that comprises a cutting region CR between the first testing module TM1 and the second testing module TM2.
Regarding claim 8, Daubenspeck teaches the via structure V1 that is free from overlapping the cutting region CR along a third direction (in and out of the page) substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 9, Daubenspeck teaches a third testing module TM3, wherein the first testing module TM1 and the third testing module TM3 that are arranged along the first direction D1.
Regarding claim 11, Daubenspeck teaches the cutting region CR that is free of metallic materials.
Regarding claim 13, Daubenspeck teaches the via structure V1 that is free from overlapping the cutting region CR along the first direction D1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck.
Regarding claim 12, Daubenspeck does not specify a width of the cutting region CR that ranges from about 0.5 [Symbol font/0x6D]m and about 3 [Symbol font/0x6D]m along the second direction D2.
However, in Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Court held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (see MPEP 2144.04).
Since the only difference between the claimed semiconductor device and the semiconductor device taught by Daubenspeck is a relative dimension the width of about 0.5 [Symbol font/0x6D]m and about 3 [Symbol font/0x6D]m, the Court would be more likely than not hold that the claimed semiconductor device is not patentably distinct from the semiconductor device taught by Daubenspeck. Moreover, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art modify the semiconductor device such the width of the cutting region that ranges about 0.5 [Symbol font/0x6D]m and about 3 [Symbol font/0x6D]m along the second direction with a reasonable expectation of providing a semiconductor device that is in the nanometer scale as the one of ordinary skill in the semiconductor art is incentivized to make adjustments to size to fit an intended purpose of making device smaller as market forces demand that the device scale down with Moore's Law.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 is objected to for depending on a rejected base claim 1 and the intervening claims 2, 7 and 8, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 10 and the intervening claims 2, 7, and 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2024/0112943 a1 to Chen et al.
Pub. No. US 2023/0140675 A1 to Kim et al.
Pub. No. US 2023/0013898 A1 to Zhang
Pub. No. US 2022/0367299 A1 to Chang et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817
04 June 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
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