DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I (claims 8-10, and 12-15) in the reply filed on 8/4/26 is acknowledged.
Claims 1-7, 11, and 16-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/4/26. Applicant is reminded that any claims that include all the limitations of an allowable claim are subject to rejoinder, and may be subsequently allowed as long as they are dependent on an allowable claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8, 9, and 12 thru 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al US 2024/0096725 A1. Park discloses (see, for example, FIG. 4) a power chip package structure 30, comprising: a first carrier 12 comprising a first ceramic board 123 and a first inner metal layer 121 formed on an inner plate surface of the first ceramic board 123, wherein the first inner metal layer 121 comprises at least one first connection pad 121t; a first self-correction layer 1112 formed on the first inner metal layer 121, wherein the first self-correction layer 1112 and at least one of the first connection pads 121t jointly form at least one first slot (i.e. area that is filled by the chip bodies 115), wherein the first self-correction layer 1112 comprises a first glue body and a plurality of first elastic spacers disposed in the first glue body; at least one first conductive paste (i.e. the unlabeled section of element 1111p that directly contacts a first bonding pad 1151/1152 of the chip body 115) 1111p filled into the at least one first slot; and a power chip 11, comprising: a chip body 115 disposed on the first self-correction layer 1112; and at least one first bonding pad 1151/1152 formed on a first surface of the chip body 115, wherein the at least one first bonding pad 1151/1152 is connected to the at least one first conductive paste 1111p, so that the power chip 11 is electrically coupled to the first carrier 12. Regarding the limitation “the first self-correction layer comprises a first glue body and a plurality of first elastic spacers disposed”, see, for example, paragraph [0065] wherein Park discloses the first self-correction layer 1112 includes polymer with fillers.
Regarding claim 9, see, for example, FIG. 4 wherein Park discloses a conductive paste 1111p, which is also formed in the slot (i.e. underneath the chip body 115) and in paragraph [0070], Park discloses that Ag sintered paste may be included.
Regarding claim 12, see, for example, FIG. 4 wherein Park discloses a second carrier 13 comprising a second ceramic board 133 and a second inner metal layer 131 formed on the inner plate surface of the second ceramic board 133, wherein the second inner metal layer 131 comprises at least one second connection pad 131t; a second self-correction layer 1122 formed on the second inner metal layer 131, wherein the second self-correction layer 1122 and the at least one second connection pad 131t jointly form at least one second slot (i.e. area that is filled by the chip bodies 115), wherein the second self-correction layer 1122 comprises a second glue body and a plurality of second elastic spacers disposed in the second glue body; and at least one second conductive paste (i.e. the portion that is directly above the chip body 115) 1121p filled into the at least one second slot; wherein the power chip 11 comprises at least one second bonding pad 1153 formed on a second surface of the chip body 115, and the second self-correction layer 1122 is disposed on the second surface of the chip body 115, wherein the at least one second bonding pad 1153 is connected to the at least one second conductive paste 1121p, so that the power chip 11 is electrically coupled to the second carrier 13. Regarding the limitation “the second self-correction layer comprises a second glue body and a plurality of second elastic spacers disposed”, see, for example, paragraph [0075] wherein Park discloses the second self-correction layer 1122 includes polymer with fillers.
Regarding claim 13, see, for example, FIG. 4 wherein Park discloses the power chip package structure 30 further comprises a plurality of pins 14-1 that are spaced apart from each other around the power chip 11 and clamped and fixed between the first carrier 12 and the second carrier 13, wherein each of the plurality of pins 14-1 is electrically coupled to the first carrier 12 and the second carrier 13.
Regarding claim 14, see, for example, FIG. 4 wherein Park discloses the first surface of the power chip 11 is completely covered by the first self-correction layer 1112 and the at least one first conductive paste 1111p, and the second surface of the power chip 11 is completely covered by the second self-correction layer 1122 and the at least one second conductive paste 1121p.
Regarding claim 15, see, for example, FIG. 4 wherein Park discloses first carrier 12 comprising a first outer metal layer 122 and inner metal layer 121 and a second carrier 13 comprising a second outer metal layer 132 and inner metal layer 131. The term “sintered” is a product-by-process limitation, and does not affect the final structure of the first inner metal layer and the first outer metal layer being fixed to the inner plate surface and an outer plate surface of the first ceramic board, and the second inner metal layer and the second outer metal layer being fixed to the inner plate surface and an outer plate surface of the second ceramic board.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al US 2024/0096725 A1 as applied to claims 8, 9, and 12-15 above. Park does not clearly disclose top edges of the plurality of elastic spacers are substantially aligned with a top surface of the first glue body and are in contact with the first surface of the power chip. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have top edges of the plurality of elastic spacers being substantially aligned with a top surface of the first glue body and being in contact with the first surface of the power chip in order to maintain a planar surface with minimized roughness while improving thermal uniformity.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
August 14, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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