DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2022/0352123) by Chen et al (“Chen”).
Regarding claim 17, Chen discloses in FIG. 8B and related text, e.g., a method of forming an integrated passive device (par. 28; “deep trench capacitor … integration”), comprising:
forming a deep trench capacitor (103) in a substrate (101);
forming electrical interconnect structures (301) on a first side (top) of the substrate;
coupling the electrical interconnect structures to the deep trench capacitor (see FIG. 8B; they are coupled to it);
forming an electrically conducting through-substrate-via (201) within the substrate such that the through-substrate-via extends from the first side of the substrate to a second side (bottom) of the substrate (see FIG. 8B); and
coupling the through-substrate-via to one or more of the electrical interconnect structures formed on the first side of the substrate (see FIG. 8B; they are coupled).
Regarding claim 18, Chen discloses in FIG. 8B and related text, e.g., further comprising:
forming an electrically conducting material layer (825) on the second side of the substrate that is formed in direct contact with the substrate (see FIG. 8B) and that is electrically connected to the through-substrate-via (see FIG. 8B);
forming a polymer layer (unmarked layer in FIG. 8B, to the sides of 825; per FIG. 8A, 809, this is “third underfill”; use of “polymer layer” for “underfill” is notoriously well-known (there are more than 5,000 results for “polymer” with “underfill”; hence, the use of “polymer” material for “underfill” application is at the very least obvious in light of Chen’s explicit teachings; also, see par. 57 of Chen, for list of possible materials) over the electrically conducting material layer (see FIG. 8B); and
forming an opening in the polymer layer (opening in “underfill” that contains 701) that exposes a portion of the electrically conducting material layer such that an exposed portion of the electrically conducting material layer is formed as an electrical contact structure on the second side of the substrate (before 701 was deposited in it, there was “an opening”; thus meeting limitations).
Regarding claim 19, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via further comprises:
forming the through-substrate-via as an electrically conducting shell structure around the deep trench capacitor that extends from the first side of the substrate to the second side of the substrate (see FIG. 8B; 201 is present on both sides of 103; hence, “electrically conducting shell”).
Regarding claim 20, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via further comprises:
forming the through-substrate-via as a composite structure comprising an electrically conducting shell structure (same as claim 19) surrounding a non-conducting polymer material (see par. 36; “any suitable dielectric material may be used” (for the liner); hence, the “polymer material”, as a liner, is going to be between the two TSVs; hence, “surrounding a non-conducting polymer material”), such that the electrically conducting shell structure is separate and distinct from the deep trench capacitor (by definition; one is capacitor and the other is TSV).
Regarding claim 21, Chen discloses in FIG. 8B and related text, e.g., a method of forming an integrated passive device (see claim 17), comprising:
forming a deep trench capacitor within a substrate (see claim 17), the deep trench capacitor having power terminals and ground terminals (by definition; unmarked, but present in FIG. 8B; the two metal pieces directly above 103);
forming electrical interconnect structures on a first side of the substrate (see claim 17), the electrical interconnect structures comprising first interconnects electrically connected to the power terminals and second interconnects electrically connected to the ground terminals (by definition; 103 is part of overall electrical circuit; hence, its “power” and “ground” terminals have proper connections);
forming an electrically conducting through-substrate-via within the substrate (see claim 17), the through-substrate-via extending from the first side of the substrate to a second side of the substrate and electrically connected to the second interconnects (see claim 17; also, it is all one electric circuit; hence, everything is electrically connected to everything else).
Regarding claim 22, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via comprises:
forming the through-substrate-via as an electrically conducting shell structure around the deep trench capacitor (see claim 19).
Regarding claim 23, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via comprises:
forming the through-substrate-via as a composite structure comprising an electrically conducting shell structure surrounding a non-conducting polymer material, wherein the electrically conducting shell structure is separate and distinct from the deep trench capacitor (see claim 20).
Regarding claim 24, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via comprises:
forming the through-substrate-via as a volume of electrically conducting material extending through the substrate (see FIG. 8B, 201; it qualifies as “volume of electrically conducting material”).
Regarding claim 25, Chen discloses in FIG. 8B and related text, e.g., further comprising:
forming a dielectric layer (see FIG. 8B, the dielectric portion of 301; apparently it is layer 107 (see par. 34)) on the first side of the substrate, wherein the electrical interconnect structures are formed within the dielectric layer (see FIG. 8B).
Regarding claim 26, Chen discloses in FIG. 8B and related text, e.g., wherein forming the through-substrate-via comprises:
forming the through-substrate-via to extend from the second side of the substrate, through the first side of the substrate, and through at least a portion of the dielectric layer (see FIG. 8B, 201; it meets all the limitations, including going through a thin dielectric layer).
Regarding claim 27, Chen discloses in FIG. 8B and related text, e.g., wherein the electrical interconnect structures are formed as redistribution layers (by definition) that further comprise micro-bump electrical contacts (401) electrically connected to respective power terminals and ground terminals (by definition; the “power” and “ground” contacts require a source; in the device of FIG. 8B, the sources are 401/701 that are interconnected to each other; thus meeting limitations).
Regarding claim 28, Chen discloses in FIG. 8B and related text, e.g., wherein:
the substrate comprises silicon (see par. 29); and
the through-substrate-via comprises an electrically conducting material formed in direct contact with the substrate (see par. 36; “the TSV openings may be lined with a liner”; liner is explicitly optional; hence, the cited embodiment is explicitly taught by Chen).
Regarding claim 29, Chen discloses in FIG. 8B and related text, e.g., a method of forming an integrated passive device (see claim 17), comprising:
forming a deep trench capacitor in a substrate (see claim 17);
forming electrical interconnect structures on a first side of the substrate and coupling the electrical interconnect structures to the deep trench capacitor (see claim 17);
forming an electrically conducting through-substrate-via within the substrate such that the through-substrate-via extends from the first side of the substrate to a second side of the substrate and is electrically connected to one or more of the electrical interconnect structures (see claim 17);
performing a grinding operation on the second side of the substrate to expose a surface of the through-substrate-via (see par. 63; “CMP”);
forming an electrically conducting material layer (FIG. 8B, 825) on the second side of the substrate in direct contact with the substrate and electrically connected to the through-substrate-via (see FIG. 8B).
Regarding claim 30, Chen discloses in FIG. 8B and related text, e.g., further comprising:
forming a polymer layer over the electrically conducting material layer (see claim 18).
Regarding claim 31, Chen discloses in FIG. 8B and related text, e.g., further comprising:
forming an opening in the polymer layer that exposes a portion of the electrically conducting material layer to form an electrical contact structure on the second side of the substrate (see claim 18).
Regarding claim 32, Chen discloses in FIG. 8B and related text, e.g., further comprising:
forming a plating layer (701; see par. 65; “electroplating”) over the exposed portion of the electrically conducting material layer (823; see pars. 64-65).
Regarding claim 33, Chen discloses in FIG. 8B and related text, e.g., wherein:
the electrically conducting material layer and the through-substrate-via comprise copper (see pars. 65 and 91); and the plating layer comprises tin (see par. 65).
Regarding claim 34, Chen discloses in FIG. 8B and related text, e.g., wherein the electrically conducting material layer is formed by electroplating (see par. 64; “any suitable materials and processes may be utilized”; hence, the use of “electroplating” is at the very least obvious in light of Chen’s explicit teachings).
Regarding claim 35, Chen discloses in FIG. 8B and related text, e.g., wherein the electrically conducting material layer is formed by a vapor phase deposition process (see claim 34; same logic applies).
Regarding claim 36, Chen discloses in FIG. 8B and related text, e.g., wherein:
the electrical interconnect structures comprise first interconnects connected to power terminals of the deep trench capacitor and second interconnects connected to ground terminals of the deep trench capacitor (see claim 21); and the through-substrate-via is electrically connected to the second interconnects (see claim 22).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/28/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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