DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May, 17, 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sung (US 2023/0164977 A1).
Claim 1, Sung discloses a method for manufacturing a semiconductor structure (semiconductor device 100/200 is semiconductor structure, hereinafter, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A), comprising:
forming a channel unit (channel material layer 16A is a channel unit, hereinafter, channel unit 16/16A/16B, [0056], Fig. 2A) on a base structure (channel unit 16/16A/16B is formed on the substrate 11, buffer layer 12, conductive layer 13A, and barrier material layer 14A which is a base structure, hereinafter, base structure 11/12, [0056], Fig. 2A), the channel unit 16/16A/16B including at least one vertical channel (channel material layer 16B is at least one vertical channel, hereinafter, at least one vertical channel 16B, [0065], Fig. 2B) which extends in a vertical direction to terminate at an upper end and a lower end of the at least one vertical channel 16B (channel unit 16/16A/16B includes at least one vertical channel 16B which extends in a vertical direction to terminate at an upper end and a lower end of the at least one vertical channel 16B, [0065], Fig. 2B);
forming a first conducting oxide unit (upper interface material layer 17/17A/17B is a first conducting oxide unit, hereinafter, first conducting oxide unit 17/17A/17B, [0062], Fig. 2B) that is disposed on and connected to the upper end of the at least one vertical channel 16B (first conducting oxide unit 17/17A/17B is disposed on and connected to the upper end of the at least one vertical channel 16B, [0062], Fig. 2B);
forming a second conducting oxide unit (lower interface material layer 15/15A/15B is a second conductive oxide unit, hereinafter, second conductive oxide unit 15/15A/15B, [0062], Fig. 2B) that is connected to the channel unit 16/16A/16B (second conductive oxide unit 15/15A/15B is connected to the channel unit 16/16A/16B, [0062], Fig. 2B) and that is spaced apart from the first conducting oxide unit 17A/17B (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B, [0062], Fig. 2B) so as to permit charge carriers to be transmitted between the first conducting oxide unit 17A/17B and the second conducting oxide unit 15A/15B through the at least one vertical channel 16B in the vertical direction (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B so as to permit charge carriers to be transmitted between the first conducting oxide unit 17A/17B and the second conducting oxide unit 15A/15B through the at least one vertical channel 16B in the vertical direction, [0062], Fig. 2B);
forming a gate dielectric (gate dielectric layer 23 is a gate dielectric, hereinafter, gate dielectric 23, [0071], Fig. 2E) over the channel unit 16, the first conducting oxide unit 17 and the second conducting oxide unit 15 (gate dielectric 23 is formed over the channel unit 16, the first conducting oxide unit 17 and the second conducting oxide unit 15 (i.e. oxide semiconductor pillars 21P, [0070]), [0071], Fig. 2E);
forming a metal gate (word line conductive layer 24/24A is a metal gate, hereinafter, metal gate 24/24A, [0072], Fig. 2E) over the gate dielectric 23 opposite to the base structure 11/12 (metal gate 24/24A is formed over the gate dielectric 23 opposite to the base structure 11/12, [0072], Fig. 2E);
recessing the metal gate 24/24A to expose the gate dielectric 23 (metal gate 24/24A is recessed to expose the gate dielectric 23, [0072], Figs. 2E and 2F); and
partially removing the gate dielectric 23 to at least expose the first conducting oxide unit 17 (partially removing the gate dielectric 23 to at least expose the first conducting oxide unit 17, [0077], Fig. 2H).
Claim 2, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 1.
Sung discloses further comprising:
forming a first metal contact unit (first contact plugs 27 are a first metal contact unit, hereinafter, first metal contact unit 27, [0078], Fig. 2I) over the recessed metal gate 24 such that the first metal contact unit 27 is connected to the first conducting oxide unit 17 (first metal contact unit 27 are formed over the recessed metal gate 24 such that the first metal contact unit 27 is connected to the first conducting oxide unit 17, [0078], Fig. 2I), and is electrically isolated from the recessed metal gate 24 (first metal contact unit 27 is electrically isolated from the recessed metal gate 24, [0078], Fig. 2I); and
prior to forming the channel unit 16/16A/16B, forming a second metal contact unit (prior to forming the channel unit 16/16A/16B, conductive layer 13A is formed into a bit line 13 which is a second metal contact unit, hereinafter, second metal contact unit 13/13A, [0065], Fig. 2B) in the base structure 11/12 (second metal contact unit 13/13A is formed in the base structure 11/12, [0065], Fig. 2B),
the second conducting oxide unit 15/15A being formed over the second metal contact unit 13/13A before forming the channel unit 16/16A/16B, such that after forming the channel unit 16/16A/16B, the lower end of the at least one vertical channel 16/16B is disposed on and connected to the second conducting oxide unit 15/15A (second conducting oxide unit 15/15A being formed over the second metal contact unit 13/13A before forming the channel unit 16/16A/16B, such that after forming the channel unit 16/16A/16B, the lower end of the at least one vertical channel 16/16B is disposed on and connected to the second conducting oxide unit 15/15A, [0065], Figs. 2A and 2B).
Claim 3, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 2.
Sung discloses wherein:
the at least one vertical channel 16/16B includes vertical channels that are spaced apart from each other in a horizontal direction transverse to the vertical direction (each of the at least one vertical channel 16/16B is a vertical channels that is spaced apart from each other in a horizontal direction transverse to the vertical direction, [0065], Fig. 2B);
forming the first conducting oxide unit 17A/17B includes forming conducting features which are respectively in direct contact with the upper end of the vertical channels 16/16B (forming the first conducting oxide unit 17A/17B includes forming conducting features which are respectively in direct contact with the upper end of the vertical channels 16/16B, [0060], Fig. 2B); and
the second conducting oxide unit 15/15A is in direct contact with the lower ends of the vertical channels 16/16B (second conducting oxide unit 15/15A is in direct contact with the lower ends of the vertical channels 16/16B, [0060], Fig. 2B).
Claim 4, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 3.
Sung discloses wherein forming the channel unit 16/16A/16B, the first conducting oxide unit 17/17A/17B and the second conducting oxide unit 15/15A includes:
sequentially forming a lower conducting oxide film 15/15A, a channel film 16/16A/16B and an upper conducting oxide film 17/17A/17B over the base structure 11/12 (lower conducting oxide film 15/15A, a channel film 16/16A/16B and an upper conducting oxide film 17/17A/17B over the base structure 11/12 are sequentially formed, [0060], Fig. 2B), the lower conducting oxide film 15/15A serving as the second conducting oxide unit 15 (lower conducting oxide film 15/15A serving as the second conducting oxide unit 15, [0060], Fig. 2B); and
performing a patterning process to form the upper conducting oxide film 17/17A/17B into the conducting features of the first conducting oxide unit 17 (a patterning process is performed to form the upper conducting oxide film 17/17A/17B into the conducting features of the first conducting oxide unit 17, [0060], Fig. 2B), and to form the channel film 16/16A/16B into the vertical channels of the channel unit 16 (a patterning process is performed to form the channel film 16/16A/16B into the vertical channels of the channel unit 16, [0060], Fig. 2B).
Claim 5, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 1.
Sung discloses wherein:
the channel unit 16/16A/16B further includes a connecting part (metal interconnection MLM is a connecting part, hereinafter, connecting part MLM, [0104], Fig. 4A) in the base structure 11/12 (channel unit 16/16A/16B further includes a connecting par MLM in the base structure 11/12, [0104], Fig. 4A), and the at least one vertical channel includes vertical channels 16/16A/16B extending from the connecting part MLM in the vertical direction opposite to the base structure 11/12 (the at least one vertical channel includes vertical channels 16/16A/16B extending from the connecting part MLM in the vertical direction opposite to the base structure 11/12, [0104], Fig. 4A), the vertical channels 16/16A/16B being spaced apart from each other in a horizontal direction transverse to the vertical direction and connected to each other through the connecting part MLM (vertical channels 16/16A/16B being spaced apart from each other in a horizontal direction transverse to the vertical direction and connected to each other through the connecting part MLM, [0104], Fig. 4A);
each of the first conducting oxide unit 17 and the second conducting oxide unit 15 being in direct contact with the upper end of a corresponding one of the vertical channels 16 (each of the first conducting oxide unit 17 and the second conducting oxide unit 15 being in direct contact with the upper end of a corresponding one of the vertical channels 16, [0067], Fig. 2D); and
after partially removing the gate dielectric 23, the first conducting oxide unit 17 and the second conducting oxide unit 15 are exposed (oxide semiconductor pillars 21P may be formed after partially removing the gate dielectric 23, wherein the first conducting oxide unit 17 and the second conducting oxide unit 15 are exposed, [0135], Figs. 7F and 7G).
Claim 6, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 5.
Sung discloses wherein forming the channel unit, the first conducting oxide unit and the second conducting oxide unit includes:
forming the connecting part (metal interconnection MLM is a connecting part, hereinafter, connecting part MLM, [0104], Fig. 4A) in the base structure (connecting part MLM is formed in the base structure 201/102/110/111, [0104], Fig. 4A);
sequentially forming a channel film 121 and a conducting oxide film 122/123 over the base structure 201/102/110/111 and the connecting part MLM (a channel film 121 and a conducting oxide film 122/123 is sequentially formed over the base structure 201/102/110/111 and the connecting part MLM); and
performing a patterning process to form the channel film 16/16A/16B into the vertical channels of the channel unit 16 (a patterning process is performed to form the channel film 16/16A/16B into the vertical channels of the channel unit 16, [0060], Fig. 2B), and to form the conducting oxide film 15A/17A into the first conducting oxide unit 17/17A and the second conducting oxide unit 15/15A (a patterning process is performed to form the conducting oxide film 15A/17A into the first conducting oxide unit 17/17A and the second conducting oxide unit 15/15A, [0060], Fig. 2B).
Claim 7, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 1.
Sung discloses further comprising,
after recessing the metal gate 24/24A, forming an insulating layer (inter-layer dielectric layer 26 is an insulating layer, hereinafter, insulating layer 26, [0078], Figs. 2H and 7F) over the recessed metal gate 24 (insulating layer 26 is formed over the recessed metal gate 24, [0078], Figs. 2H and 7F), and
before partially removing the gate dielectric 23, partially removing the insulating layer 26 so as to expose the gate dielectric 23 (partially removing the insulating layer 26 so as to expose the gate dielectric 23 before partially removing the gate dielectric 23, [0133], Fig. 7F).
Claim 17, Sung discloses a semiconductor structure (semiconductor device 100/200 is semiconductor structure, hereinafter, semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A), comprising:
a channel unit (channel material layer 16A is a channel unit, hereinafter, channel unit 16/16A/16B, [0056], Fig. 2A) disposed on a base structure (channel unit 16/16A/16B is formed on the substrate 11, buffer layer 12, conductive layer 13A, and barrier material layer 14A which is a base structure, hereinafter, base structure 11/12, [0056], Fig. 2A), and including atomic layers that are stacked on each other along a vertical direction (channel material layer 16B includes atomic layers that are stacked on each other along a vertical direction, [0065], Fig. 2B);
a gate dielectric (gate dielectric layer 23 is a gate dielectric, hereinafter, gate dielectric 23, [0071], Fig. 2E) disposed on the base structure 11/12 and surrounding the channel unit 16 (gate dielectric 23 is disposed on the base structure 11/12 and surrounding the channel unit 16, the first conducting oxide unit 17 and the second conducting oxide unit 15 (i.e. oxide semiconductor pillars 21P, [0070]), [0071], Fig. 2E);
a metal gate (word line conductive layer 24/24A is a metal gate, hereinafter, metal gate 24/24A, [0072], Fig. 2E) disposed on the gate dielectric 23 (metal gate 24/24A is disposed on the gate dielectric 23, [0072], Fig. 2E);
a first conducting oxide unit (upper interface material layer 17/17A/17B is a first conducting oxide unit, hereinafter, first conducting oxide unit 17/17A/17B, [0062], Fig. 2B) that is in direct contact with the channel unit 16 (first conducting oxide unit 17/17A/17B is in direct contact with the channel unit 16, [0062], Fig. 2B); and
a second conducting oxide unit (lower interface material layer 15/15A/15B is a second conductive oxide unit, hereinafter, second conductive oxide unit 15/15A/15B, [0062], Fig. 2B) that is in direct contact with the channel unit 16/16A/16B (second conductive oxide unit 15/15A/15B is connected to the channel unit 16/16A/16B, [0062], Fig. 2B) and that is spaced apart from the first conducting oxide unit 17A/17B (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B, [0062], Fig. 2B) so as to permit charge carriers to be transmitted between the first conducting oxide unit 17A/17B and the second conducting oxide unit 15A/15B through the atomic layers of the channel unit 16B along the vertical direction (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B so as to permit charge carriers to be transmitted between the first conducting oxide unit 17A/17B and the second conducting oxide unit 15A/15B through the atomic layers of the channel unit 16B along the vertical direction, [0062], Fig. 2B).
Claim 18, Sung discloses the semiconductor structure (semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 17.
Sung discloses further comprising:
a first metal contact unit (first contact plugs 27 are a first metal contact unit, hereinafter, first metal contact unit 27, [0078], Fig. 2I) that is connected to the first conducting oxide unit 17 (first metal contact unit 27 is connected to the first conducting oxide unit 17, [0078], Fig. 2I) so as to permit the first metal contact unit 27 to be in ohmic or Schottky contact with the channel unit 16/16A/16B through the first conducting oxide unit 17 (first metal contact unit 27 is connected to the first conducting oxide unit 17 so as to permit the first metal contact unit 27 to be in ohmic or Schottky contact with the channel unit 16/16A/16B through the first conducting oxide unit 17, [0078], Fig. 2I); and
a second metal contact unit (conductive layer 13A is formed into a bit line 13 which is a second metal contact unit, hereinafter, second metal contact unit 13/13A, [0065], Fig. 2B) that is connected to the second conducting oxide unit 15 so as to permit the second metal contact 13 unit to be in ohmic or Schottky contact with the channel unit 16/16A/16B through the second conducting oxide unit 15 (second metal contact unit 13/13A is connected to the second conducting oxide unit 15 so as to permit the second metal contact 13 unit to be in ohmic or Schottky contact with the channel unit 16/16A/16B through the second conducting oxide unit 15, [0065], Fig. 2B).
Claim 19, Sung discloses the semiconductor structure (semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 17.
Sung discloses wherein the channel unit 16/16A/16B includes vertical channels that are spaced apart from each other along a horizontal direction transverse to the vertical direction (each of the at least one vertical channel 16/16B is a vertical channels that is spaced apart from each other in a horizontal direction transverse to the vertical direction, [0065], Fig. 2B), each of the vertical channels having an upper end and a lower end opposite to each other along the vertical direction (each of the vertical channels 16B of the channel unit 16/16A/16B extends in a vertical direction having an upper end and a lower end opposite to each other along the vertical direction, [0065], Fig. 2B).
Claim 20, Sung discloses the semiconductor structure (semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 17.
Sung discloses wherein the first conducting oxide unit 17 and the second connecting oxide unit 15 are located opposite to each other in the vertical direction (first conducting oxide unit 17 and the second connecting oxide unit 15 are located opposite to each other in the vertical direction, [0065], Fig. 2B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Lee (US 2023/0389290 A1).
Claim 8, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 7.
Sung does not explicitly disclose wherein after partially removing the insulating layer and partially removing the gate dielectric, a top surface of the first conducting oxide unit is flush with a top surface of the partially removed insulating layer.
However, Lee discloses wherein after partially removing the insulating layer and partially removing the gate dielectric, a top surface of the first conducting oxide unit is flush with a top surface of the partially removed insulating layer (Lee, after partially removing the insulating layer 50 and partially removing the gate dielectric 24_1, a top surface of the first conducting oxide unit 9_1 is flush with a top surface of the partially removed insulating layer 50, [0062], Fig. 1; Sung, after partially removing the insulating layer 26 and partially removing the gate dielectric 23, a top surface of the first conducting oxide unit 17 is in contact with a top surface of the partially removed insulating layer 26, Fig. 7G). The combination to utilize the above lying insulating layer to be flush with the upper most conducting oxide unit enables for improved charge mobility and on-current properties, as well as resultant semiconductor devices having a high degree of integration and an improved electrical performance (Lee, [0122]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the above lying insulating layer to be flush with the upper most conducting oxide unit enables for improved charge mobility and on-current properties, as well as resultant semiconductor devices having a high degree of integration and an improved electrical performance (Lee, [0122]).
Claim 9, Sung/Lee discloses the method (Sung, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A; Lee, Fig. 1) as claimed in claim 8.
Sung/Lee discloses further comprising, forming a conducting oxide portion over the top surface of the partially removed insulating layer and the first conducting oxide unit (Sung, forming a conducting oxide portion 37 over the top surface of the partially removed insulating layer 26 and the first conducting oxide unit 17A/17B, [0094], Fig. 3B and 4A; Lee, Fig. 1).
Claim 10, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 7.
Sung discloses wherein after partially removing the insulating layer, the first conducting oxide unit has a protruding portion protruding away from a top surface of the partially removed insulating layer, and the method further comprises forming a first metal contact unit that surrounds the protruding portion.
However, Lee discloses Sung discloses wherein after partially removing the insulating layer, the first conducting oxide unit has a protruding portion protruding away from a top surface of the partially removed insulating layer, and the method further comprises forming a first metal contact unit that surrounds the protruding portion (Lee, after partially removing the insulating layer 115, the first conducting oxide unit 16/170 has a protruding portion 170 protruding away from a top surface of the partially removed insulating layer 115, and the method further comprises forming a first metal contact unit 192 that surrounds the protruding portion 170, [0049], Fig. 2A; Sung, insulating layer 26 and first conducting oxide unit 17, Fig. 4A). The combination to utilize the above lying insulating layer to be underlying with the upper most conducting oxide unit (i.e. protruding) enables for improved charge mobility and on-current properties, as well as resultant semiconductor devices having a high degree of integration and an improved electrical performance (Lee, [0122]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the above lying insulating layer to be underlying with the upper most conducting oxide unit (i.e. protruding) enables for improved charge mobility and on-current properties, as well as resultant semiconductor devices having a high degree of integration and an improved electrical performance (Lee, [0122]).
Claim 11, Sung discloses the method (method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A) as claimed in claim 1.
Sung does not explicitly disclose wherein the at least one vertical channel is made of a material such that the charge carriers are transmitted in the vertical direction by a first speed and in a horizontal direction by a second speed, the horizontal direction being transverse to the vertical direction, the first speed being faster than the second speed
However, Lee discloses wherein the at least one vertical channel is made of a material such that the charge carriers are transmitted in the vertical direction by a first speed and in a horizontal direction by a second speed, the horizontal direction being transverse to the vertical direction, the first speed being faster than the second speed (Lee, tin monoxide (SnO) is known in the art to have a hole mobility in the vertical direction higher than that in the horizontal direction, [0025], Fig. 2A; Sung, oxide semiconductor material is used for the oxide semiconductor channel and interface layers, [0041], Fig. 4A). The combination to utilize a conductive oxide material have a variable hole mobility depending on the orientation of the crystal lattice would ensure proper deposition of the channel layer such that the oxide material may be used as a channel material to suppress gate-induced drain leakage and junction leakage so as to improve retention characteristics (Sung, [0185]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a conductive oxide material to have a variable hole mobility depending on the orientation of the crystal lattice would ensure proper deposition of the channel layer such that the oxide material may be used as a channel material to suppress gate-induced drain leakage and junction leakage so as to improve retention characteristics (Sung, [0185]).
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Song (US 2024/0072175 A1).
Claim 12, Sung discloses a method for manufacturing a semiconductor structure (semiconductor device 100/200 is semiconductor structure, hereinafter, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A), comprising:
depositing atomic layers of a channel material (channel material layer 16A is a channel unit, hereinafter, channel unit 16/16A/16B, [0056], Fig. 2A) on a base structure along a vertical direction (channel unit 16/16A/16B is formed on the substrate 11, buffer layer 12, conductive layer 13A, and barrier material layer 14A which is a base structure, hereinafter, base structure 11/12 along a vertical direction, [0056], Fig. 2A);
patterning the atomic layers of channel material into a channel unit (a patterning process is performed to form the channel film 16/16A/16B into the vertical channels of the channel unit 16, [0060], Fig. 2B);
forming a first conducting oxide unit (upper interface material layer 17/17A/17B is a first conducting oxide unit, hereinafter, first conducting oxide unit 17/17A/17B, [0062], Fig. 2B) that is connected to the channel unit (first conducting oxide unit 17/17A/17B is connected to the channel unit 16, [0062], Fig. 2B);
forming a second conducting oxide unit (lower interface material layer 15/15A/15B is a second conductive oxide unit, hereinafter, second conductive oxide unit 15/15A/15B, [0062], Fig. 2B) that is connected to the channel unit (second conductive oxide unit 15/15A/15B is connected to the channel unit 16/16A/16B, [0062], Fig. 2B) and that is spaced apart from the first conducting oxide unit (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B, [0062], Fig. 2B) so as to permit charge carriers to be transmitted between the first conducting oxide unit and the second conducting oxide unit through the patterned atomic layers in the channel unit along the vertical direction (second conductive oxide unit 15/15A/15B is spaced apart from the first conducting oxide unit 17A/17B so as to permit charge carriers to be transmitted between the first conducting oxide unit 17A/17B and the second conducting oxide unit 15A/15B through the channel unit 16/16A/16 in the vertical direction, [0062], Fig. 2B);
forming a gate dielectric (gate dielectric layer 23 is a gate dielectric, hereinafter, gate dielectric 23, [0071], Fig. 2E) over the channel unit, the first conducting oxide unit and the second conducting oxide unit (gate dielectric 23 is formed over the channel unit 16, the first conducting oxide unit 17 and the second conducting oxide unit 15 (i.e. oxide semiconductor pillars 21P, [0070]), [0071], Fig. 2E);
forming a metal gate (word line conductive layer 24/24A is a metal gate, hereinafter, metal gate 24/24A, [0072], Fig. 2E) over the gate dielectric opposite to the base structure (metal gate 24/24A is formed over the gate dielectric 23 opposite to the base structure 11/12, [0072], Fig. 2E);
recessing the metal gate to expose the gate dielectric (metal gate 24/24A is recessed to expose the gate dielectric 23, [0072], Figs. 2E and 2F); and
partially removing the gate dielectric to expose at least the first conducting oxide unit (partially removing the gate dielectric 23 to at least expose the first conducting oxide unit 17, [0077], Fig. 2H).
Sung does not explicitly disclose depositing atomic layers of tin monoxide (SnO) on a base structure along a vertical direction; and patterning the atomic layers of tin monoxide into a channel unit.
However, Song discloses depositing atomic layers of tin monoxide (SnO) (Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A; Sung, channel material layer 16A is a channel unit, hereinafter, channel unit 16/16A/16B, [0056], Fig. 2A) on a base structure along a vertical direction (Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO) on a base structure along a vertical direction, [0043] and [0045], Fig. 2A; Sung, channel unit 16/16A/16B is formed on the substrate 11, buffer layer 12, conductive layer 13A, and barrier material layer 14A which is a base structure, hereinafter, base structure 11/12 along a vertical direction, [0056], Fig. 2A); and
patterning the atomic layers of tin monoxide into a channel unit (Song, main channel portion 120 and channel contact portion 122 may be patterned and form a channel unit of atomic layers of tin oxide (i.e. tin monoxide, SnO) on a base structure along a vertical direction, [0043] and [0045], Figs. 14C and 16A; Sung, a patterning process is performed to form the channel film 16/16A/16B into the vertical channels of the channel unit 16, [0060], Fig. 2B). The combination to utilize tin monoxide as a conductive channel material in combination with a plurality of channel contact portions provides an improvement in the resultant semiconductor device having reduce contact resistance between the channel unit and electrically adjacent conductive contacts (Song, [0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize tin monoxide as a conductive channel material in combination with a plurality of channel contact portions provides an improvement in the resultant semiconductor device having reduce contact resistance between the channel unit and electrically adjacent conductive contacts (Song, [0004]).
Claim 13, Sung/Song discloses the method (Sung, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A; Song, Fig. 2A) as claimed in claim 12.
Sung/Song discloses wherein the channel unit includes vertical channels (Sung, channel unit 16/16A/16B includes the channel material layer 16B which is at least one vertical channel, hereinafter, vertical channels 16B, [0065], Fig. 2B; Song, Fig. 2A) that are spaced apart from each other along a horizontal direction transverse to the vertical direction (Sung, channel unit 16/16A/16B includes vertical channels 16B which are spaced apart from each other along a horizontal direction transverse to the vertical direction, [0065], Fig. 2B; Song, Fig. 2A), each of the vertical channels having an upper end and a lower end opposite to each other along the vertical direction (Sung, channel unit 16/16A/16B includes vertical channels 16B which extends in a vertical direction to terminate at an upper end and a lower end opposite to each other along the vertical direction, [0065], Fig. 2B; Song, Fig. 2A).
Claim 14, Sung/Song discloses the method (Sung, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A; Song, Fig. 2A) as claimed in claim 13.
Sung/Song discloses wherein the first conducting oxide unit includes conducting features (Sung, first conducting oxide unit 17/17A/17B includes conducting features, [0062], Fig. 2B; Song, Fig. 2A), and forming the first conducting oxide unit includes (Sung, forming the first conducting oxide unit 17/17A/17B, [0062], Fig. 2B; Song, Fig. 2A):
prior to patterning the atomic layers of tin monoxide, forming an upper conducting oxide film over the atomic layers of tin monoxide (Sung, first conducting oxide unit 17/17A/17B is an upper conducting oxide film that is formed over the atomic channel layers prior to patterning the atomic channel layers, [0062], Fig. 2B; Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A); and
patterning the upper conducting oxide film into the conducting features (Sung, upper conducting oxide film 17/17A/17B is patterned into the conducting features, [0062], Fig. 2B; Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A),
the atomic layers of tin monoxide being patterned into the vertical channels through the conducting features (Sung, atomic channel layers are patterned into the vertical channels through the conducting features, [0062], Fig. 2B; Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A).
Claim 15, Sung/Song discloses the method (Sung, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A; Song, Fig. 2A) as claimed in claim 13.
Sung/Song discloses wherein the first conducting oxide unit and the second conducting oxide unit are formed by, prior to patterning of the atomic layers of tin monoxide, depositing a conducting oxide film over the atomic layers of tin monoxide (Sung, first conducting oxide unit 17/17A/17B and second conductive oxide unit 15/15A/15B are formed by, prior to patterning the atomic channel layers, depositing a conductive oxide film 15A/17A over the atomic channel layers, [0062], Fig. 2B; Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A), and performing a patterning process to form the conducting oxide film into the first conducting oxide unit and the second conducting oxide unit (Sung, first conducting oxide unit 17/17A/17B and second conductive oxide unit 15/15A/15B are formed by performing a patterning process to form the conducting oxide film 15A/17A into the first conducting oxide unit 17/17A/17B and the second conducting oxide unit 15/15A/15B, [0062], Fig. 2B; Song, main channel portion 120 and channel contact portion 122 may be formed by depositing atomic layers of tin oxide (i.e. tin monoxide, SnO), [0043] and [0045], Fig. 2A).
Claim 16, Sung/Song discloses the method (Sung, method for manufacturing a semiconductor structure 100/200, [0031] and [0100], Figs. 2A-2K and 4A; Song, Fig. 2A) as claimed in claim 12.
Sung/Song discloses further comprising, after partially removing the gate dielectric (Sung, partially removing the gate dielectric 23 to at least expose the first conducting oxide unit 17, [0077], Fig. 2H; Song, Fig. 2A), forming a conducting oxide portion over the exposed first conducting oxide unit (Sung, forming a conducting oxide portion 37 over the exposed first conducting oxide unit 17A/17B, [0094], Fig. 3B and 4A; Song, Fig. 2A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Doornbos (US 2021/0375887 A1) discloses a semiconductor structure D500, comprising: a channel unit 108/208 disposed on a base structure 102, and including atomic layers that are stacked on each other along a vertical direction; a gate dielectric 106/206 disposed on the base structure 102 and surrounding the channel unit 108/208; and a metal gate 104’/204 disposed on the gate dielectric 106/206;
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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