DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed March 12, 2062 has been entered. Claims 1-2 and 6-27 remain pending in this application. Claims 3-5 have been cancelled at applicant’s request. Claims 1, 16-17, and 21-22 have been amended. Claims 25-27 have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed December 12, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 and 6-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0026463 A1 to Shyam Sundar (hereafter Sundar) in view of US 6,583,648 B1 to Zhong-Ning Cai (hereafter Cai) and further in view of US 2019/0101952 A1 to Mitchell Diamond, et al. (hereafter Diamond).
Regarding Amended Independent Claim 1, Sundar discloses a system, comprising:
a first storage element (A first storage element: Sundar, ¶[0027]) comprising
a plurality of data storage locations (The first storage element comprising data memory: Sundar, ¶[0027]);
a second storage element (Physical Register PR: Sundar, Figure 4) comprising
an array of bits (PR comprising a series of bits: Sundar, ¶[0064])
indicating an availability (The free list 330 displaying availability: Sundar, ¶[0064])
for a corresponding data storage location in the plurality of data storage locations (The free list tracking availability of physical locations: Sundar, ¶[0064]); and
a first set of bits to be read or written (Executing a next available instruction: Sundar, ¶[0080])
in response to being activated by a first clock gating signal (In response to a clock cycle: Sundar, ¶[0080]); and
a second set of bits to be read or written (Executing a next available instruction: Sundar, ¶[0080])
in response to being activated by a second clock gating signal (In response to a clock cycle: Sundar, ¶[0080]).
While Sundar discloses a free index flop array, comprising a storage element indicating data storage location availability, it does not expressly disclose a control circuit including a first and second switching element for selectively enabling sets of bits. Cai, however, discloses a memory device as in claim 1, including:
a control circuit (A circuit providing a clock distribution network: Cai, col.2:54-55) comprising:
at least a first switching element (A first clock gating circuit: Cai, col.3:23-24)
coupled to a first set of bits in the array of bits (The first clock gating circuit coupled to a first set of circuits: Cai, Figure 2),
wherein the at least a first switching element selectively enables the first set of bits (Selectively enabling the first circuits: Cai, col.3:19-22); and
at least a second switching element (A second clock gating circuit: Cai, Figure 2)
coupled to a second set of bits in the array of bits (Selectively enabling the second circuits: Cai, col.3:19-22),
wherein the at least a second switching element selectively enables the second set of bits (Selectively enabling the second circuits: Cai, col.3:19-22).
Cai teaches selective switching elements for clock gating allows the clock signal to propagate at a regular frequency, at a substantially reduced frequency, or be completely disabled (Cai, col.2:50-53). Cai further teaches clock gating for reduced power consumption is common in the art (Cai, col.1:18-25). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to apply the commonly known power conservation clock gating of Cai to the free index flop array of Sundar, with a reasonable expectation of success. Both inventions are well known in the field of memory array management and the combination of known inventions with predictable results is obvious and not patentable.
Sundar and Cai fail to explicitly disclose the number of bits in the first set of bits is different from a number of bits in the second set of bits. Diamond, however, discloses a clock gating circuit as in Claim 1, wherein a number of bits in the first set of bits is different from a number of bits in the second set of bits (Disclosing the clock gating circuit may selectively enable one or more components, including in any combination: Diamond, ¶[0117]; Note: The designation of ‘First’ and ‘Second’ number of bits is arbitrary. If the number of bits in two groups are different, it is inherent that one of the groups is larger than the other. Similarly, if the number of bits in one group is less than the number of bits in the other, then it is inherent the number of bits in the groups are different).
Diamond teaches this method of customized clock gating groups allows certain clocked components to be utilized or not, based on the configuration (Diamond, ¶[0117]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the customizable clock gate group size of Diamond with the power conservation clock gating of Cai, with a reasonable expectation of success. Both inventions are well known in the field of clock gating circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Cai discloses the system of claim 1, wherein the at least a first switching element and the at least a second switching element
are connected to a common ungated clock signal (Disclosing a high-level clock gating circuit generating enabling/disabling signals from a common global clock: Cai, col.3:57-64).
Regarding Claim 6, Cai discloses the system of claim 1, wherein the at least a first switching element comprises
a first digital logic element and wherein the at least a second switching element comprises a second digital logic element (Disclosing an exemplar switching element comprising a digital logical element: Cai, Figure 3).
Regarding Claim 7, Sundar discloses the system of claim 1, wherein
the first storage element comprises multiple storage sub-elements (The memory system comprising multiple subsystems: Sundar, Figure 1) and
wherein the second storage element comprises multiple storage sub-elements (The free index flop array comprising a series of free index lists 430a-430b: Sundar, ¶[0064]).
Regarding Claim 8, Sundar discloses the system of claim 1, wherein
the first set of bits is activated (Opening the list to retrieve instructions: Sundar, ¶[0059]) with the first clock gating signal (Activating and enacting the instruction in time with a clock signal: Sundar, ¶[0080]) and
enabled to be read to identify a state of a first set of data storage locations in the first storage element (The list including a state of the data in the first set of storage: Sundar, Figure 2).
Regarding Claim 9, Sundar discloses the system of claim 8, wherein
the first set of bits (Activating the list to retrieve instructions: Sundar, ¶[0059]) is activated with the first clock gating signal (Activating and enacting the instruction in time with a clock signal: Sundar, ¶[0080]) and
enabled to be written to update state of a first set of data storage locations in the first storage element (The list including a state of the data in the first set of storage: Sundar, Figure 2).
Regarding Claim 10, Sundar discloses the system of claim 9, wherein
one or more writes are performed to a free index flop array (Updating the free list: Sundar, ¶[0074])
at a given time to update a status of data storage locations (Updating the status of the storage locations in the free list: Sundar, ¶[0074]).
Regarding Claim 11, Sundar and Cai disclose the system of claim 8, wherein
the second set of bits is activated with the second clock gating signal (Selectively enabling the second circuits: Cai, col.3:19-22) and
enabled to be read
to identify a state of a second set of data storage locations in the first storage element (The list including a state of the data in the first set of storage: Sundar, Figure 2) and
wherein the second clock gating signal operates independent of the first clock gating signal (Each clock gating circuit may be activated independently and individually: Cai, col.7:55-58).
Regarding Claim 12, Sundar discloses the system of claim 1, wherein the first storage element comprises
a readable and writable memory device (The first storage element being an updatable memory system: Sundar, ¶[0027]).
Regarding Claim 13, Sundar discloses the system of claim 12, wherein the first storage element comprises
a Random Access Memory (RAM) device (The first storage element being a random access memory device: Sundar, ¶[0027]).
Regarding Claim 14, Sundar discloses the system of claim 1, wherein
the array of bits is provided as part of a flop array or flop vector or array of flops (Disclosing an array “separate from the free list” used for maintaining duplicate mappings for registers, suggesting the free list is an array: Sundar, ¶[0007]; Note, no distinction between a flop array, a flop vector, and an array of flops is made in the specification and other references treat the terms as fungible. Therefore, the terms will be treated as equivalent).
Regarding Claim 15, Diamond discloses the system of claim 1, wherein
the first set of bits are activated to be read (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0125])
with the first clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0125])
when data from a corresponding first set of data storage locations in the plurality of data storage locations is to have data read therefrom (Activating the relevant circuits on output: Diamond, ¶[0125]) and
wherein the second set of bits are activated to be read (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0125])
with the second clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0125])
when data from a corresponding second set of data storage locations in the plurality of data storage locations is to have data read therefrom (Activating the relevant circuits on output: Diamond, ¶[0125]).
Regarding Amended Claim 16, Diamond discloses the system of claim 1, wherein
the first set of bits are activated to be written (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
with the first clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0124])
when data to a corresponding first set of data storage locations in the plurality of data storage locations is written (Activating the relevant circuits on input: Diamond, ¶[0124]) and
wherein the second set of bits are activated to be written (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
with the second clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0124])
when data to a corresponding second set of data storage locations in the plurality of data storage locations is to be written (Activating the relevant circuits on input: Diamond, ¶[0124]).
Regarding Amended Independent Claim 17, Sundar discloses a control circuit to selectively activate an array of bits, wherein
the array of bits (PR comprising a series of bits: Sundar, ¶[0064]) indicate an availability (The free list 330 displaying availability: Sundar, ¶[0064]) for data storage locations in a storage element (The free list tracking availability of physical locations: Sundar, ¶[0064]),
A first set of bits to be read or written (Executing a next available instruction: Sundar, ¶[0080])
in response to activation by a first clock gating signal (In response to a clock cycle: Sundar, ¶[0080]); and
A second set of bits to be read or written (Executing a next available instruction: Sundar, ¶[0080])
in response to activation by a second clock gating signal (In response to a clock cycle: Sundar, ¶[0080]).
While Sundar discloses a free index flop array, comprising a storage element indicating data storage location availability, it does not expressly disclose a control circuit including a first and second switching element for selectively enabling sets of bits. Cai, however, discloses a memory device as in claim 1, including:
a control circuit (A circuit providing a clock distribution network: Cai, col.2:54-55) comprising:
at least a first switching element (A first clock gating circuit: Cai, col.3:23-24)
coupled to a first set of bits in the array of bits (The first clock gating circuit coupled to a first set of circuits: Cai, Figure 2),
wherein the at least a first switching element selectively enables the first set of bits (Selectively enabling the first circuits: Cai, col.3:19-22); and
at least a second switching element (A second clock gating circuit: Cai, Figure 2)
coupled to a second set of bits in the array of bits (Selectively enabling the second circuits: Cai, col.3:19-22),
wherein the at least a second switching element selectively enables the second set of bits (Selectively enabling the second circuits: Cai, col.3:19-22)
in response to activation by a second clock gating signal that is different from the first clock gating signal (Disclosing the second signal is a separate signal from the first signal: Cia, col.3:17-19)
Cai teaches selective switching elements for clock gating allows the clock signal to propagate at a regular frequency, at a substantially reduced frequency, or be completely disabled (Cai, col.2:50-53). Cai further teaches clock gating for reduced power consumption is common in the art (Cai, col.1:18-25). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to apply the commonly known power conservation clock gating of Cai to the free index flop array of Sundar, with a reasonable expectation of success. Both inventions are well known in the field of memory array management and the combination of known inventions with predictable results is obvious and not patentable.
Sundar and Cai fail to explicitly disclose the number of bits in the first set of bits is different from a number of bits in the second set of bits. Diamond, however, discloses a clock gating circuit as in Claim 1, wherein a number of bits in the first set of bits is different from a number of bits in the second set of bits (Disclosing the clock gating circuit may selectively enable one or more components, including in any combination: Diamond, ¶[0117]; Note: The designation of ‘First’ and ‘Second’ number of bits is arbitrary. If the number of bits in two groups are different, it is inherent that one of the groups is larger than the other. Similarly, if the number of bits in one group is less than the number of bits in the other, then it is inherent the number of bits in the groups are different).
Diamond teaches this method of customized clock gating groups allows certain clocked components to be utilized or not, based on the configuration (Diamond, ¶[0117]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the customizable clock gate group size of Diamond with the power conservation clock gating of Cai, with a reasonable expectation of success. Both inventions are well known in the field of clock gating circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Sundar discloses the control circuit of Claim 17, discloses the system of claim 1, wherein
the first set of bits
are activated to be read or written (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
with the first clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0124])
when data from a corresponding first set of data storage locations
is to have data read therefrom (Activating the relevant circuits on output: Diamond, ¶[0125]) or to be written (Activating the relevant circuits on input: Diamond, ¶[0124]),
wherein the second set of bits
are activated to be read or written (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
with the second clock gating signal (Aligning register enablement to the clock signal: Diamond, ¶[0124])
when data from a corresponding second set of data storage locations
is to have data read therefrom (Activating the relevant circuits on output: Diamond, ¶[0125]) or written to (Activating the relevant circuits on input: Diamond, ¶[0124]),
wherein the first set of bits is non-overlapping with the second set of bits (Illustrating the register arrays are non-overlapping: Cai, Figure 2), and
wherein the first set of data storage locations is non-overlapping with the second set of data storage locations (Disclosing the free list contains a number of entries equal to the number of physical register numbers, therefore demonstrate lack of duplication or overlap: Sundar, ¶[0055]).
Regarding Claim 19, Diamond discloses the control circuit of claim 18, wherein
the first set of bits
are deactivated in an absence of the first clock gating signal (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
when data from the corresponding first set of data storage locations
is not to have data read therefrom or no data to be written (Activating the relevant circuits only on output: Diamond, ¶[0125]) and
wherein the second set of bits
are deactivated in an absence of the second clock gating signal (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0124])
when data from the corresponding second set of data storage locations is not to have data read therefrom or no data to be written (Activating the relevant circuits only on output: Diamond, ¶[0125]).
Regarding Claim 20, Sundar discloses the control circuit of claim 17, wherein
a number of bits in the array of bits is equal to a number of data storage locations in the storage element (Disclosing the free list contains a number of entries equal to the number of physical register numbers: Sundar, ¶[0055]).
Regarding Amended Claim 21, Cai discloses the control circuit of claim 17, wherein
the array of bits of bits is divided into a number of subgroups (The register being divided into a number of subgroups: Cai, col.7:15-17) and
wherein each subgroup in the number of subgroups
is provided with a corresponding switching element (Providing a corresponding switching element to each circuit: Cai, Figure 2)
to manage a clock gate provided to the corresponding subgroup (Where each subgroup is controlled by a clock gate: Cai, col.2:54-55).
Regarding Amended Independent Claim 22, Sundar discloses a semiconductor device, comprising:
an array of bits (PR comprising a series of bits: Sundar, ¶[0064]) indicating an availability (The free list 330 displaying availability: Sundar, ¶[0064]) for a corresponding data storage location (The free list tracking availability of physical locations: Sundar, ¶[0064]) in a data storage element (A storage element: Sundar, ¶[0027]).
While Sundar discloses a free index flop array, comprising a storage element indicating data storage location availability, it does not expressly disclose the array being divided into subgroups of bits or a control circuit including a switching elements for selectively enabling sets of bits. Cai, however, discloses a memory device as in claim 22, including:
wherein the array of bits is divided into a number of subgroups (Dividing the controlled circuitry into a number of subgroups: Cai, Figure 2); and
a control circuit (A circuit providing a clock distribution network: Cai, col.2:54-55) to manage clock gating for the array of bits (The clock gating circuit coupled to a set of circuits: Cai, Figure 2),
wherein the control circuit provides a separate clock gating signal (Providing separate clock gating signals depending on path: Cai, 3:4-7)
to each subgroup of bits in the array of bits (Selectively enabling the second circuits: Cai, col.3:19-22)
to independently control when each subgroup is activated (Each clock gating circuit may be activated independently and individually: Cai, col.7:55-58)
Cai teaches selective switching elements for clock gating allows the clock signal to propagate at a regular frequency, at a substantially reduced frequency, or be completely disabled (Cai, col.2:50-53). Cai further teaches clock gating for reduced power consumption is common in the art (Cai, col.1:18-25). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to apply the commonly known power conservation clock gating of Cai to the free index flop array of Sundar, with a reasonable expectation of success. Both inventions are well known in the field of memory array management and the combination of known inventions with predictable results is obvious and not patentable.
Sundar and Cai fail to explicitly disclose the number of bits in the first set of bits is different from a number of bits in the second set of bits. Diamond, however, discloses a clock gating circuit as in Claim 1, wherein a number of bits in the first set of bits is different from a number of bits in the second set of bits (Disclosing the clock gating circuit may selectively enable one or more components, including in any combination: Diamond, ¶[0117]; Note: The designation of ‘First’ and ‘Second’ number of bits is arbitrary. If the number of bits in two groups are different, it is inherent that one of the groups is larger than the other. Similarly, if the number of bits in one group is less than the number of bits in the other, then it is inherent the number of bits in the groups are different).
Diamond teaches this method of customized clock gating groups allows certain clocked components to be utilized or not, based on the configuration (Diamond, ¶[0117]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the customizable clock gate group size of Diamond with the power conservation clock gating of Cai, with a reasonable expectation of success. Both inventions are well known in the field of clock gating circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 23, Diamond discloses the semiconductor device of claim 22, wherein
each subgroup,
in an absence of receiving a clock-enable (CE) signal from the control circuit (Gating circuits in the absence of a signal: Diamond, ¶[0122]),
is deactivated and requires less power (Deactivating a register when not accessing the register, implying the inverse: Diamond, ¶[0125])
as compared to when the subgroup is activated with a CE signal (Disclosing deactivating unused circuitry saves power: Diamond, ¶[0119]).
Regarding Claim 24, Cai discloses the semiconductor device of claim 22, wherein the control circuit comprises
a number of switching elements equal to the number of subgroups (Disclosing each Local Clock Enable circuit connected to an equal number of sub-circuits: Cai, col.7:25) and
wherein each switching element is used to selectively control whether a clock-enable (CE) signal is provided to a corresponding subgroup (Circuits being selectively controlled in accordance with a clock enable signal: Cai, col.4:58-67).
Regarding New Claim 25, Diamond discloses the semiconductor device of claim 22, wherein
the first subgroup of bits receives a first clock gating signal and wherein the second subgroup of bits receives a second clock gating signal (Disclosing data storage elements 404 receiving a first clock gating signal and data storage elements 406 receiving a separate second gating signal: Diamond, ¶[0117]) .
Regarding New Claim 26, Sundar discloses the semiconductor device of claim 22, wherein
a number of bits in the array of bits is equal to a number of data storage locations in the data storage element (Teaching the free list has a number of entries equal to the number of physical register numbers: Sundar, ¶[0055]).
Regarding New Claim 27, Cai discloses the semiconductor device of claim 22, wherein
each subgroup of bits is connected to a different switching element to manage the clock gating signal provided thereto (Disclosing separate regional and local clock gating signals: Cai, col.4:63-67).
Response to Arguments
Applicant's arguments filed March 12, 2026 have been fully considered but they are not persuasive.
As a preliminary note, Applicant states in their remarks, “While no agreement was reached regarding allowable subject matter, the Examiners suggested that incorporation of the features recited in the originally-filed claim 5 would overcome the current objections and could likely place the application in condition for allowance.” (Applicant Arguments/Remarks, page 8 ¶3). This overstates the Examiner’s understanding of the interview. As stated in the Examiner’s Interview Summary, “Applicant suggested clarifying the relationship, or distinction, between the switching elements and the array of bits, such as by incorporating limitations from dependent claims 4 and/or 5. Examiner agreed this would help move examination forward.” This distinction is not trivial. ‘Moving the examination forward,’ merely anticipates overcoming the present, as written, claim limitations. If the Applicant interpreted this phrase to mean, “likely to place in condition for allowance,” that interpretation was not intended and was in error.
In either case, both Applicant and Examiner agreed any final determination would depend on the exact wording of amendments and be subject to additional examination and search. In the present instance, Applicant’s amendment incorporates the limitations of Claim 5 into claim 1 without further clarifying the relationship or distinction between the switching elements and the array of bits, a stated requirement of “moving the examination forward.”
In regards to Applicant’s arguments, Applicant and Examiner agree Sundar discloses first and second storage elements, the first comprising a plurality of data storage locations and the latter an array of bits indicating availability for corresponding data storage locations. All parties also agree Sundar fails to disclose a control circuit having first and second switching elements (Applicants Arguments and Remarks, page 10 ¶1). In the prior office action, Examiner argued prior art Cai may be used to resolve this omission.
Applicant argues Cai fails to disclose the first and second switching elements, as claimed. More specifically, Applicant argues the switching elements are not disclosed as coupled to different bits in an array of bits (Applicants Arguments and Remarks, page 10 ¶1). Cai, however, expressly discloses the clock gating/switching elements being used to control local logic circuits (See, for instance, Cai, Figure 4 and Figure 5; See also, Disclosing gated clock signals being used to drive, non-exclusively, LCB circuits, pairs of inputs, and latch circuits). In the present specification, Applicant refers to the index array alternatively as ‘Free index logic’ and buffers, which may be logically equated with the logic and latches of Cai. Therefore, applicant’s argument is unpersuasive.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,133,577 B2 to Jesus Corbal, et al.: Teaching a memory device processor with an instruction scheduler to selectively enable first data elements for operations.
US 7,065,665 B2 to Hans M. Jacobson, et al.: Teaching a circuit with a clock gating system whereby clock signals are stalled at various tiers of enablement.
US 2014/0129745 A1 to Robert A. Alfieri: Teaching a latch array and a RAM array, with the latch array being assigned a higher priority, and therefore fist access, than the RAM array.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824