Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 05/17/24. Claims 1-20 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. §103 as being unpatentable over Xu (CN114622183), and further in view of Cho (US 20190272999 A1).
Regarding claim 1, Xu discloses a method comprising: exposing a semiconductor substrate to a silicon-containing precursor and an oxygen-containing plasma to deposit a silicon oxide (SiOx) film, wherein the oxygen-containing plasma is a microwave plasma generated by a microwave plasma source (see claims 1 and 4 disclosing microwave plasma forming silicon oxide film).
However, Xu does not explicitly disclose: a microwave plasma source including a plasma showerhead assembly comprising a conductive plate and a dielectric faceplate, a plurality of resonator openings through the conductive plate, and a dielectric resonator in each of the plurality of resonator openings. However, Cho is directed towards process chamber features and at least at fig 6 discloses a microwave plasma source including a plasma showerhead assembly comprising a conductive plate (see para [0039] disclosing conductive) and a dielectric faceplate (see para [0081]), a plurality of resonator openings through the conductive plate (see fig 6a), and a dielectric resonator in each of the plurality of resonator openings (see fig 6 disclosing openings and para [0090] disclosing resonance.)
Xu and Cho are in the same or similar fields of endeavor. It would have been obvious to on having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Xu with Cho. Xu and Cho may be combined by forming the conductive face plate and dielectric layer of Cho in the device of Xu. One having ordinary skill in the art would be motivated to combine Xu and Cho in order to perform plasma treatment.
Regarding claim 2, Xu and Cho disclose the method of claim 1, performed at a temperature in a range of from 100 °C to 700 °C (see claim 3 disclosing 500c).
Regarding claim 3, Xu and Cho disclose the method of claim 1, comprising a plasma-enhanced atomic layer deposition (PEALD) process (see claim 1 disclosing plasma enhanced ald).
Regarding claim 4, Xu and Cho disclose the method of claim 1, wherein the oxygen-containing plasma comprises one or more of oxygen (O2), ozone (O3), or nitrous oxide (N2O) (see claim 5 disclosing oxygen species).
Regarding claim 5, Xu and Cho disclose at least at para [0010], discloses the method of claim 1, comprising exposing the semiconductor substrate to the silicon-containing precursor for a time period in a range of from 0.1 seconds to 60 seconds ( see para [0010], 0-20ms).
Regarding claim 6, Xu and Cho disclose the method of claim 1, comprising exposing the semiconductor substrate to the oxygen-containing plasma for a time period in a range of from 0.1 seconds to 120 seconds (see para [0010], 0-20ms).
Regarding claim 7, Xu and Cho disclose the method of claim 1, further comprising exposing the semiconductor substrate to a treatment plasma(see para [0010], 0-20ms, treatment plasma).
Regarding claim 8, Xu and Cho disclose the method of claim 7, wherein the treatment plasma is a microwave plasma generated by a microwave plasma source(see claims 1 and 4 disclosing microwave plasma forming silicon oxide film).
Regarding claim 9, Xu and Cho disclose the method of claim 7, wherein the treatment plasma comprises oxygen (O2) and one or more of nitrogen (N2), argon (Ar), or helium (He) (see claim 5 disclosing oxygen and N2).
Regarding claim 10, Xu and Cho disclose the method of claim 9, wherein the treatment plasma consists essentially of oxygen (O2) and nitrogen (N2) (see claim 5 disclosing oxygen and N2).
Regarding claim 11, Xu and Cho disclose the method of claim 9, wherein the treatment plasma consists essentially of oxygen (O2) and argon (Ar) (see claim 5 disclosing oxygen and Ar).
Regarding claim 12, Xu and Cho disclose the method of claim 9, wherein the treatment plasma consists essentially of oxygen (O2) and helium (He) (see claim 5 disclosing oxygen and He).
Regarding claim 13, Xu and Cho disclose the method of claim 7, comprising exposing the semiconductor substrate to the treatment plasma for a time period in a range of from 0.1 seconds to 120 seconds(see para [0010], 0-20ms).
Regarding claim 14, Xu and Cho disclose, at least at fig 1, the method of claim 1, wherein the semiconductor substrate comprises at least one feature, the at least one feature defining a trench having a top surface, a bottom surface, and two sidewalls (see fig 1 disclosing trenches with features).
Regarding claim 15, Xu and Cho disclose a method of manufacturing a semiconductor device, the method comprising:
exposing a semiconductor substrate to a silicon-containing precursor (see claim 1 disclosing silicon oxide source) and an oxygen-containing plasma to deposit a silicon oxide (SiOx) film (see claim 1 disclosing SiOx film)wherein the oxygen-containing plasma comprises one or more of oxygen (O2), ozone (O3), or nitrous oxide (N2O) (see claims 1, 3, 5, disclosing laughing gas), the oxygen-containing plasma is a microwave plasma generated by a microwave plasma source, and the method is performed at a temperature in a range of from 100 °C to 700 °C (see para [0045] and claim 4, claim 3 disclosing 500c).
Regarding claim 16, Xu and Cho disclose the method of claim 15, comprising exposing the semiconductor substrate to the silicon-containing precursor for a time period in a range of from 0.1 seconds to 60 seconds and exposing the semiconductor substrate to the oxygen-containing plasma for a time period in a range of from 0.1 seconds to 120 seconds (see para [0010], 0-20ms).
Regarding claim 17, Xu and Cho disclose the method of claim 15, further comprising exposing the semiconductor substrate to a treatment plasma, the treatment plasma comprising a microwave plasma including oxygen (O2) and one or more of nitrogen (N2), argon (Ar), or helium (He) (see claim 5 disclosing N2, Ar or He).
Regarding claim 18, Xu and Cho disclose the method of claim 17, comprising exposing the semiconductor substrate to the treatment plasma for a time period in a range of from 0.1 seconds to 120 seconds (see para [0010], 0-20ms).
Claims 19 and 20 are rejected under 35 U.S.C. §103 as being unpatentable over Xu and Cho as applied to claim 15 and further in view of Suzuki (US 20230343587 A).
Regarding claim 19, Xu and Cho disclose the method of claim 15, but does not explicitly disclose wherein the semiconductor device includes a 3D-NAND structure.
However, Suzuki, at least at para [0002] discloses 3d-NAND. Xu, Cho and Suzuki are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Xu and Cho with Suzuki. Xu, Cho and Suzuki may be combined by forming the device of Xu and Cho into a memory device disclosed in Suzuki. One having ordinary skill in the art would be motivated to combine Xu and Cho and Suzuki in order to form a memory device.
Regarding claim 20, Xu and Cho disclose the method of claim 15, and Suzuki further discloses wherein the semiconductor device includes a dynamic random-access memory (DRAM) structure (see para 40 disclosing memory).
It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Xu and Cho with Suzuki. Xu, Cho and Suzuki may be combined by forming the device of Xu and Cho into a memory device disclosed in Suzuki. One having ordinary skill in the art would be motivated to combine Xu, Cho and Suzuki in order to form a memory device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
