DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 102 3
A. Claims 1, 2, 8, 11-16, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0201667 (“Chen”). 3
III. Claim Rejections - 35 USC § 103 7
A. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2013/0270690 (“Hsieh”). 7
B. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2020/0105644 (“Teng”) and as evidenced by US 2025/0019535 (“Yamamoto”). 8
C. Claims 1, 2, 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0130761 (“Kim”) in view of Chen. 9
IV. Pertinent Prior Art 16
Conclusion 17
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1, 2, 8, 11-16, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0201667 (“Chen”).
With regard to claim 1, Chen discloses, generally in Figs. 3 and 4,
1. A packaged integrated circuit device 101 [¶ 46], comprising:
[1a] a first semiconductor substrate 10 [¶¶ 33-35, 47] that includes:
[1b] an integrated circuit [¶¶ 33-34, e.g. the integrated circuit forming logic devices and memory devices and RAM, DRAM, EDRAM, PCM, FLASH memory],
[1c] a region of signal layers 5 residing on a first side [top side in Figs. 3 and 4] of the first semiconductor substrate 10 [¶ 39: “The first back end of the line (BEOL) level 5 may be a multilayered level of dielectric interlevel dielectrics having metal lines for horizontal electrical communication and metal vias for vertical electrical communication present therein.”], and
[1d] a region of power delivery layers 20 residing on a second side [back side in Figs. 3 and 4] of the first semiconductor substrate 10 [¶ 39: “The back side interconnect 20 may be a component of a back side power distribution network.”]; and
[2a] a second semiconductor substrate 51 [¶¶ 27, 39] coupled to the region of signal layers 5, wherein
[2b] a first side [back side in Figs. 3 and 4] of the second semiconductor substrate 51 is coupled to the region of signal layers 5, and
[2c] a second side [top side in Figs. 3 and 4] of the second semiconductor substrate 51 includes a plurality of fluidic channels 53 [¶¶ 24, 36, 37].
With regard to claim 2, Chen further discloses,
2. The packaged integrated circuit device of claim 1, further comprising a lid structure 52 that is coupled to the second side [top side in Figs. 3 and 4] of the second semiconductor substrate 51 and encloses the plurality of fluidic channels 53.
With regard to claims 8, 11, and 12, Chen further discloses,
8. The packaged integrated circuit device of claim 1, further comprising a heat-spreader layer [infra] disposed on the first side [back side in Figs. 3 and 4] of the second semiconductor substrate 51.
11. The packaged integrated circuit device of claim 8, wherein the heat-spreader layer contacts [infra] one or more heat-transfer vias 50 included in the second semiconductor substrate 51.
12. The packaged integrated circuit device of claim 1, wherein the second semiconductor substrate 51 includes one or more heat-transfer vias 50.
The heat spreader layer is delineated in the annotated version of Fig. 3 and includes the lateral extensions from the “second thermal cooling through silicon vias 50” in the BEOL layer 5 (¶¶ 24, 26, 32). The lateral extensions of thermally conductive material, i.e. metal (¶ 32) in Fig. 3 of Chen, is consistent with the heat spreader layer 701 shown in Fig. 7 of the Instant Application.
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(Annotated Fig. 3 of Chen)
With regard to claim 13, Chen further discloses,
13. The packaged integrated circuit device of claim 12, wherein the one or more heat-transfer vias 50 are disposed proximate to a processing core 10 of the integrated circuit [¶¶ 33-34, e.g. the integrated circuit forming logic devices and memory devices and RAM, DRAM, EDRAM, PCM, FLASH memory].
With regard to claim 14, Chen further discloses,
14. The packaged integrated circuit device of claim 1, wherein the fluidic channels 53 comprise an array of projections that reside on the second side [top side in Figs. 3 and 4] of the second semiconductor substrate 51.
With regard to claim 15, Chen discloses, generally in Figs. 3 and 4,
15. A card-based processing subsystem comprising:
[1] a printed circuit board [not given a reference character but includes “ball metallurgy 60” and “electrical pathways 61” (¶¶ 50-51)]; and
[2] a packaged integrated circuit device 101 that is mounted on the printed circuit board and comprises:
[3a] a first semiconductor substrate 10 that includes:
[3b] an integrated circuit [¶¶ 33-34, e.g. the integrated circuit forming logic devices and memory devices and RAM, DRAM, EDRAM, PCM, FLASH memory],
[3c] a region of signal layers 5 residing on a first side [top side in Figs. 3 and 4] of the first semiconductor substrate, and
[3d] a region of power delivery layers 20 residing on a second side [bottom side in Figs. 3 and 4] of the first semiconductor substrate 10; and
[4a] a second semiconductor substrate 51 coupled to the region of signal layers 5, wherein
[4b] a first side [bottom side in Figs. 3 and 4] of the second semiconductor substrate 51 is coupled to the region of signal layers, and
[4c] a second side [top side in Figs. 3 and 4] of the second semiconductor substrate 51 includes a plurality of fluidic channels 53.
16. The card-based processing subsystem of claim 15, further comprising a lid structure 52 that is coupled to the second side [top side in Figs. 3 and 4] of the second semiconductor substrate 51 and encloses the plurality of fluidic channels 53.
20. The card-based processing subsystem of claim 15, further comprising a heat-spreader layer [see annotated Fig. 3, supra] disposed on the first side [bottom side in Figs. 3 and 4] of the second semiconductor substrate 51.
III. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2013/0270690 (“Hsieh”).
Claim 3 reads,
3. The packaged integrated circuit device of claim 2, wherein the lid structure comprises a material having a first coefficient of thermal expansion that matches a second coefficient of thermal expansion of a material included in the second semiconductor substrate.
The prior art of Chen, as explained above, discloses each of the features of claims 1 and 2.
Chen does not provide the material of the lid 52 or how it is attached to the microchannel substrate 51.
Hsieh, like Chen, teaches a method of cooling an integrated circuit die 40 by attaching to said die 40 a heat-sink silicon substrate 54 having microchannels 64 etched therein for liquid coolant flow and a lid 72 attached to said heat-sink silicon substrate 54 (Hsieh: Fig. 4; ¶¶ 14-18). Hsieh further teaches that the lid 72 is made from silicon (Hsieh: ¶ 11) which, consequently, has the same CTE as the for being made from the same material as the heat-sink silicon substrate 54.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the lid 52 of Chen from the same material as that of the second substrate 51, i.e. silicon, because Hsieh teach that silicon for each of the lid and microchannel substrate is suitable for the identical purpose. As such, the selection of silicon for the lid 52 of Chen amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claim 3.
B. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2020/0105644 (“Teng”) and as evidenced by US 2025/0019535 (“Yamamoto”).
Claim 4 reads,
4. The packaged integrated circuit device of claim 2, wherein
[1] the lid structure comprises a material having a first coefficient of thermal expansion that does not match a second coefficient of thermal expansion of a material included in the second semiconductor substrate, and
[2] the lid structure is coupled to the second side of the second semiconductor substrate via an elastic material.
The prior art of Chen, as explained above, discloses each of the features of claims 1 and 2.
Chen does not provide the material of the lid 52 or how it is attached to the microchannel substrate 51.
Teng, like Chen, teaches a method of cooling a silicon integrated circuit die 111 (Teng: ¶ 14) by etching microchannels 117A for liquid coolant flow and a lid 121 attached over said microchannels 117A (Teng: Fig. 15; ¶¶ 19, 30, 36). The lid 121 is made of a metal such as copper, aluminum, or steel (Teng: ¶ 30), which is a different material from silicon and therefore has a different CTE than that of the silicon die 111. Teng attaches the lid 121 to the integrated circuit die 111 using an “first sealing member 122” that “serves as stress buffer between the chip package 110 and the side wall 121a of the heat spreader 121” (Teng: ¶ 30) and is made of polybutylacrylate (PBA) (id.), which is inherently elastic, as evidenced by the fact that it is a stress buffer between two very rigid materials, i.e. silicon and one of copper, aluminum, and steel. Additional evidence is provided by Yamamoto, which states that PBA is inherently elastic (¶ 44: “The polybutylacrylate rubber is an elastic body containing 50% by mass to 100% by mass of a butylacrylate unit in 100% by mass of structural units thereof.”) Therefore, it is held, absent evidence to the contrary that the PBA used in Teng is elastic. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the lid 52 of Chen from a metal such as copper, aluminum, or steel, i.e. silicon, because Teng teach that metal for the lid over a silicon microchannel substrate is suitable for the identical purpose. As such, the selection of metal for the lid 52 of Chen amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claim 4.
C. Claims 1, 2, 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0130761 (“Kim”) in view of Chen.
Claims 1, 2, 12, and 14 reads,
1. A packaged integrated circuit device, comprising:
[1a] a first semiconductor substrate that includes:
[1b] an integrated circuit,
[1c] a region of signal layers residing on a first side of the first semiconductor substrate, and
[1d] a region of power delivery layers residing on a second side of the first semiconductor substrate; and
[2a] a second semiconductor substrate coupled to the region of signal layers, wherein
[2b] a first side of the second semiconductor substrate is coupled to the region of signal layers, and
[2c] a second side of the second semiconductor substrate includes a plurality of fluidic channels.
2. The packaged integrated circuit device of claim 1, further comprising a lid structure that is coupled to the second side of the second semiconductor substrate and encloses the plurality of fluidic channels.
12. The packaged integrated circuit device of claim 1, wherein the second semiconductor substrate includes one or more heat-transfer vias.
14. The packaged integrated circuit device of claim 1, wherein the fluidic channels comprise an array of projections that reside on the second side of the second semiconductor substrate.
With regard to claims 1, 12, and 14, Kim discloses, generally in Figs. 3, 4, and 12,
1. A packaged integrated circuit device 110, comprising:
[1a] a first semiconductor substrate 10(SBL1)/CEL [¶¶ 30, 36, 37] that includes:
[1b] an integrated circuit CEL [¶¶ 36-37],
[1c] a region of signal layers WIL [¶ 43] residing on a first side 10a [¶ 30] of the first semiconductor substrate 10(SBL1)/CEL, and
[1d] a region of power delivery layers PDN [¶ 47] residing on a second side 10b [¶ 30] of the first semiconductor substrate 10(SBL1)/CEL; and
[2a] a second semiconductor substrate 40(SBL2) coupled to the region of signal layers WIL, wherein
[2b] a first side [back side of 40 in Figs. 4 and 12] of the second semiconductor substrate 40(SBL2) is coupled to the region of signal layers WIL, and
[2c] … [not taught] …
2. … [not taught] …
12. … [not taught] …
14. … [not taught] …
Kim discloses that heat is transferred to from the active layer CEL and the PDN the heat-sink, dummy silicon substrate 40 (Kim: ¶¶ 46, 90-91; Figs. 12-13).
Kim lacks the fluidic channels in the heat-sink dummy substrate 40 required by feature [2c] of claim 1 and the heat-transfer vias of claim 12.
As explained above, Chen, like Kim, teaches the same semiconductor device package configuration. Chen further teaches the thermal-cooling TSVs 50, i.e. the claimed “heat-transfer vias” and the microchannels 53, created by the “array of projections [shown but not labeled in Fig. 3 of Chen] that reside on the second side of the second semiconductor substrate 51”, for liquid coolant flow, enabling heat transfer away from the semiconductor package (Chen: ¶¶ 29, 36, 37).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to configure the second semiconductor substrate 40 of Kim as that in Chen to include the fluidic channels 53 formed by the “array of projections that reside on the second side of the second semiconductor substrate 51” as well as the lid 52, and the thermal-cooling TSVs 50 of Chen, in order to aid in heat removal from the package, as taught in Chen (supra). As such, Chen may be seen as an improvement to Kim in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 1, 2, 12, and 14.
With regard to claims 5-10, Kim further discloses,
5. The packaged integrated circuit device of claim 1, wherein the region of power delivery layers PDN includes a plurality of power rails 17a, 17b, PRA, GRA for distributing power to the integrated circuit [¶¶ 36-40, 58; Figs. 3, 4, 12].
6. The packaged integrated circuit device of claim 5, wherein each power rail 17a in the plurality of power rails 17a, 17b, PRA, GRA is electrically coupled to a through-silicon via 14, 22 included in the first semiconductor substrate 10(SBL1)/CEL.
7. The packaged integrated circuit device of claim 1, wherein the first semiconductor substrate 10(SBL1)/CEL includes a plurality of through-silicon vias 14, 22 that are electrically coupled to the region of power delivery layers PDN.
8. The packaged integrated circuit device of claim 1, further comprising a heat-spreader layer 62 and/or 66 disposed on the first side [back side in Figs. 4 and 12] of the second semiconductor substrate 40 [¶¶ 63-67].
9. The packaged integrated circuit device of claim 8, wherein the heat-spreader layer 62 and/or 66 comprises chemical-vapor deposition diamond, silver (Ag), copper (Cu), gold (Au), aluminum nitride (AlN), silicon carbide (SiC), aluminum (Al), tungsten (W), or graphite [Kim: ¶ 65].
10. The packaged integrated circuit device of claim 8, wherein the heat-spreader layer is disposed proximate to a processing core C1, C2, … Cn of the integrated circuit [of the first substrate 10(SBL1)/CEL].
With regard to claim 10, Kim further teaches that the semiconductor device 110 shown in Figs. 4 and 12 can be used as the processing cores C1, C2, … Cn in the semiconductor chip 300 (Kim: Fig. 20, ¶¶ 117-118). Thus, the heat-spreader layer 62 and/or 66 of Kim is “proximate” to the processing cores C1, C2, … Cn in the first substrate 10(SBL1)/CEL of Kim to every extent that said heat-spreader layer vias 710 of the Instant Application (Fig. 7) is near the processing core of “the integrated circuit” of claim 10 which is in the first substrate 300 of the Instant Application (Fig. 7), as required by instant claim 1.
With regard to claim 11, Kim modified according to Chen, as explained under claim 1, further teaches,
11. The packaged integrated circuit device of claim 8, wherein the heat-spreader layer 62 and/or 66 [of Kim] contacts one or more heat-transfer vias [50 of Chen used in Kim (supra)] included in the second semiconductor substrate 40 [of Kim modified to include the microchannels 53 and TSVs 50 of Chen (supra)].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the heat-transfer vias 50 of Chen used in Kim to the bonding pads 62, 66 of Kim in order to connect the heat transfer paths 28 (Kim: ¶ 42) to microchannels 53 of Chen used in Kim, in order to aid in removing the heat from the semiconductor device, as explained under claim 1. This is consistent with the configuration in Chen that shows the TSVs 50 are physically connected to the signal wiring layer 5.
This is all of the limitations of claim 11.
Claim 13 reads,
13. The packaged integrated circuit device of claim 12, wherein the one or more heat-transfer vias are disposed proximate to a processing core of the integrated circuit [of the first substrate].
As explained under claims 1 and 12, above, Kim modified according to Chen teaches the heat-transfer vias 50 of Chen in the second substrate 40 of Kim configured as the second substrate 51 of Chen.
Kim further teaches that the semiconductor device 110 shown in Figs. 4 and 12 can be used as the processing cores C1, C2, … Cn in the semiconductor chip 300 (Kim: Fig. 20, ¶¶ 117-118). Thus, the heat-transfer vias 50 of Chen used in the second substrate of Kim/Chen are “proximate” to the processing cores C1, C2, … Cn in the first chip 10(SBL1)/CEL of Kim to every extent that said heat transfer vias 750 of the Instant Application (Fig. 7) are near the processing core of “the integrated circuit” of claim 13 which is in the first substrate 300 of the Instant Application (Fig. 7), as required by instant claim 1.
This is all of the limitations of claim 13.
Claim 15 reads,
15. A card-based processing subsystem comprising:
[1] a printed circuit board; and
[2] a packaged integrated circuit device that is mounted on the printed circuit board and comprises:
[3a] a first semiconductor substrate that includes:
[3b] an integrated circuit,
[3c] a region of signal layers residing on a first side of the first semiconductor substrate, and
[3d] a region of power delivery layers residing on a second side of the first semiconductor substrate; and
[4a] a second semiconductor substrate coupled to the region of signal layers, wherein
[4b] a first side of the second semiconductor substrate is coupled to the region of signal layers, and
[4c] a second side of the second semiconductor substrate includes a plurality of fluidic channels.
With regard to claim 15, Kim discloses,
15. A card-based processing subsystem comprising:
[1] … [not taught] …
[2] a packaged integrated circuit device 100 …
[3a] a first semiconductor substrate 10(SBL1)/CEL [¶¶ 30, 36, 37] that includes:
[3b] an integrated circuit CEL [¶¶ 36-37],
[3c] a region of signal layers WIL [¶ 43] residing on a first side 10a [¶ 30] of the first semiconductor substrate 10(SBL1)/CEL, and
[3d] a region of power delivery layers PDN [¶ 47] residing on a second side 10b [¶ 30] of the first semiconductor substrate 10(SBL1)/CEL; and
[4a] a second semiconductor substrate 40(SBL2) coupled to the region of signal layers WIL, wherein
[4b] a first side [back side of 40 in Figs. 4 and 12] of the second semiconductor substrate 40(SBL2) is coupled to the region of signal layers WIL, and
[4c] … [not taught] …
With regard to feature [4c] of claim 15,
[4c] a second side of the second semiconductor substrate includes a plurality of fluidic channels.
This is the same as feature [2c] of claim 1 and is obvious in view of Chen for the same reasons as explained above under claim 1.
With regard to features [1] and [2] of claim 1,
[1] a printed circuit board; and
[2] a packaged integrated circuit device that is mounted on the printed circuit board and comprises:
While Kim shows “external connection terminals 60”, e.g. solder balls, that include power, ground, and signal terminals (Kim: ¶¶ 48, 91-93) but does not show to what said terminals 60 are connected.
As explained above, Chen teaches that the semiconductor package 101 is mounted on a printed circuit board (PCB) (shown in Fig. 4 but not labeled) by terminals 59 (Chen: Figs. 3, 4; ¶¶ 50-51).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to mount the semiconductor device package of Kim to a PCB in order to provide a support capable of transferring the power, ground, and signal voltages to the integrated circuit transistors CEL, as taught in Chen.
This is all of the limitations of claim 15.
Claim 16 reads,
16. The card-based processing subsystem of claim 15, further comprising a lid structure that is coupled to the second side of the second semiconductor substrate and encloses the plurality of fluidic channels.
The limitations of claim 16 are the same as in claim 2 which is obvious in view of Chen for the reasons explained above under claims 1, 2, 12, and 14, above.
With regard to claims 17-20, Kim further discloses,
17. The card-based processing subsystem of claim 15, wherein the region of power delivery layers PDN includes a plurality of power rails 17a, 17b, PRA, GRA for distributing power to the integrated circuit [¶¶ 36-40, 58; Figs. 3, 4, 12].
18. The card-based processing subsystem of claim 17, wherein each power rail 17a in the plurality of power rails 17a, 17b, PRA, GRA is electrically coupled to a through-silicon via 14, 22 included in the first semiconductor substrate 10(SBL1)/CEL.
19. The card-based processing subsystem of claim 15, wherein the first semiconductor substrate 10(SBL1)/CEL includes a plurality of through-silicon vias 14, 22 that are electrically coupled to the region of power delivery layers PDN.
20. The card-based processing subsystem of claim 15, further comprising a heat-spreader layer 62 and/or 66 disposed on the first side [bottom side in Figs. 4 and 12 of Kim] of the second semiconductor substrate 40 [of Kim/Chen].
IV. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0201669 (“Yang”) is cited for disclosing each of the features of at least claims 1 and 15. See Figs. 1-4G and 6, and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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