Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
`This office action is in response to applicant’s communication filed on 05/17/24. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information Disclosure statement filed on 05/17/24 has been received and are being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, 15 and 18 are rejected under 35 U.S.C. §103 as being unpatentable over Cho (KR 20210086274 A).
Regarding claim 1, Cho, at least at fig 4a/b discloses a display device comprising: an active layer 321a; a gate electrode disposed on the active layer 324; a first insulating layer disposed on the gate electrode (113 covering 324), entirely covering the gate electrode (see fig 4c disclosing113 covering 324), and including a flat surface (see 113 includes flatness); and a second insulating layer disposed on the first insulating layer (see114 is on 113) and including a flat surface (see fig 4b disclosing flat), wherein the first insulating layer and the second insulating layer include inorganic materials different from each other (113 is silicon nitride (SiNx) or silicon oxide (SiOx) and 114 is combination of silicon nitride (SiNx) or silicon oxide (SiOx) or multilayer, formed at different/distinct processes).
Regarding claim 2, Cho discloses the display device according to claim 1, wherein the active layer and the gate electrode are spaced apart from each other (324 and 321 are spaced apart), the display device further comprises a first gate insulating layer 112 and a second gate insulating layer 113 disposed on the active layer 321, and the gate electrode includes a first gate electrode disposed on the first gate insulating layer (324 on 112)and a second gate electrode disposed on the second gate insulating layer (510 on 113).
Regarding claim 3, Cho discloses the display device according to claim 2, wherein the flat surface of the first insulating layer does not have a step difference (see 114 does not have step on top surface).
Regarding claim 4, Cho discloses the display device according to claim 3, wherein the flat surface of the first insulating layer faces the second insulating layer (see 114a/b).
Regarding claim 5, Cho discloses the display device according to claim 3, wherein the first insulating layer is directly disposed on the second gate electrode (see 114 formed on 510).
Regarding claim 6, Cho discloses the display device according to claim 3, wherein the flat surface of the first insulating layer does not contact the second gate electrode see 114b does not touch 510.
Regarding claim 7, Cho discloses the display device according to claim 5, wherein the first insulating layer includes silicon oxide, and the second insulating layer includes silicon nitride (see description disclosing : The second buffer lower layer 114a may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) ).
Regarding claim 8, Cho discloses the display device according to claim 1, further comprising: an interlayer conductive layer disposed on the second insulating layer, wherein one surface and another surface of the interlayer conductive layer are flat (see fig 4d disclosing 116).
Regarding claim 9, Cho discloses the display device according to claim 8, wherein the interlayer conductive layer comprises: a first layer; a second layer disposed on the first layer; and a third layer disposed on the second layer, and the first layer contacts the second insulating layer (see 323, 160, 170).
Regarding claim 10, Cho discloses the display device according to claim 9, wherein the first layer and the third layer include a same material, the second layer includes a material different from the material of the first layer and the third layer, and the second layer includes aluminum (The auxiliary electrode 160 may include any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum, see description1).
Regarding claim 11, Cho discloses a method of manufacturing a display device, the method comprising: patterning an active layer on a base layer (see fig 4a/b where 321a is patterned); patterning a gate electrode on the active layer (see fig 4a/b 324 is patterned);
depositing a pre-polishing insulating layer on the gate electrode (see formation of 114a); polishing the pre-polishing insulating layer to form a first insulating portion (see fig 4a, disclosing 114 may be planarized by a chemical-mechanical polishing process); and
forming a second insulating portion on the first insulating portion 114b, wherein the first insulating portion and the second insulating portion form a first insulating layer (see 114), wherein the patterning the gate electrode on the active layer comprises:
forming a first gate electrode 234; and
forming a second gate electrode on the first gate electrode 510, wherein the first gate electrode and the second gate electrode are spaced apart from the active layer (see fig 4b disclosing 324 and 510 spaced apart from 321), and wherein in the depositing the pre-polishing insulating layer on the gate electrode, the pre-polishing insulating layer contacts the second gate electrode (see 114a contacts 510).
Regarding claim 12, Cho discloses the method according to claim 11, wherein in the polishing the pre-polishing insulating layer to form the first insulating portion, the pre-polishing insulating layer is polished using a polishing device using a slurry (see description disclosing, while supplying the slurry, the pad may be in contact with the stepped portion to apply pressure while removing the stepped portion to make it planarized), and
the first insulating portion forms a flat polish surface (see 114).
Regarding claim 15, Cho discloses the method according to claim 12, wherein in the polishing the pre-polishing insulating layer to form the first insulating portion, the pre-polishing insulating layer is polished to form the flat polish surface (see fig 4, 114a/b disclosing flat interface), and
the flat polish surface is disposed on a plane different from one surface of the second gate electrode, (see fig 4, disclosing that 510 is lower than 114a).
Regarding claim 18, Cho discloses the method according to claim 12, wherein in the polishing the pre-polishing insulating layer to form the first insulating portion, the pre-polishing insulating layer is polished to form the flat polish surface (see 114a/b disclosing flat interface), and
the flat polish surface is disposed on a same plane as one surface of the second gate electrode (see 114a and 510 having flat surfaces).
Claim Rejections under 35 U.S.C §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13, 19 are rejected under 35 U.S.C. §103 as being unpatentable over Cho as applied to claim 12 and further in view of Okada (CN 107527791 A).
Regarding claim13, Cho discloses the method according to claim 12, further comprising:
forming a second insulating layer on the second insulating portion (see 114a/b); and
forming an interlayer conductive layer on the second insulating layer(see 160, formed on 114),
wherein in the forming the interlayer conductive layer on the second insulating layer, Okada discloses the interlayer conductive layer is etched by an etching solution including a chlorine radical (see claim 2).
Cho and Okada are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Cho with Okada. Cho and Okada may be combined by forming the via holes of Cho in accordance with Okada, using chlorine species etchant. One having ordinary skill in the art would be motivated to combine Cho with Okada in order to etch a contact hole.
Regarding claim 19, Cho discloses the method according to claim 18, wherein the slurry includes ceria (see para [0019] of Okada, disclosing ceria). Cho and Okada are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Cho with Okada. Cho and Okada may be combined by forming the via holes of Cho in accordance with Okada, using chlorine species etchant. One having ordinary skill in the art would be motivated to combine Cho with Okada in order to etch a contact hole.
Claims 14 is rejected under 35 U.S.C. §103 as being unpatentable over Cho.
Regarding claim 14, Cho discloses the method according to claim 13, wherein in the depositing the pre-polishing insulating layer on the gate electrode, the pre-polishing insulating layer is deposited to have a thickness of 5500 ang to 8250 ang, as well within the capabilities of one having ordinary skill in the art.
Claims 16, and 17 are rejected under 35 U.S.C. §103 as being unpatentable over Cho and further in view of Huang (US 20200135538 A1).
Regarding claim 16, Cho discloses the method according to claim 15, and Huang discloses wherein the slurry includes silica (see para 0019 disclosing silica as cmp slurry component), and
the pre-polishing insulating layer is polished during a predetermined polishing time (see para [0016] disclosing duration calculus). Including silica and setting polish duration are well within the capabilities of one having ordinary skill in the art.
Regarding claim 17, Cho discloses the method according to claim 16, wherein in the polishing the pre-polishing insulating layer to form the first insulating portion, the first insulating portion is polished to have a thickness of 500 ang to 1000 ang in an area overlapping the first gate electrode and the second gate electrode, as well within the capabilities of one having ordinary skill in the art.
Claim 20 are rejected under 35 U.S.C. §103 as being unpatentable over Cho, Okada and further in view of Huang.
Regarding claim 20, Cho and Okada disclose the method according to claim 19, wherein the first insulating layer includes silicon oxide see description disclosing : The second buffer lower layer 114a may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), and
the slurry has a selectivity of 1:30 to 1:50 based on the second gate electrode: the silicon oxide (see para [0029] of Huang disclosing selective etching according to the silicon oxide).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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