DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/17/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 14-16 are objected to because of the following informalities:
In claims 14-16, each line 1, the limitation of “semiconductor structure” should be corrected into “structure”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 9-12, 14, 17 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 11-12, 14 and 20 of U.S. Patent No. 12,020,989 in view of Tsai (US 2019/0067277).
Regarding claim 1, Pat ‘989 discloses, in claim 14, a semiconductor structure, comprising:
a plurality of fin structures formed on a substrate; a gate structure disposed on the plurality of fin structures; a fill structure within the gate structure and disposed between two adjacent fin structures of the plurality of fin structures, the fill structure comprising: a silicon nitride liner; a silicon oxide fill layer on the silicon nitride liner; and an air gap within the silicon oxide fill layer ("fin structures disposed on a substrate; a gate structure on the fin structures; and a fill structure between adjacent fin structures, wherein the fill structure divides the gate structure into sections spaced apart by the fill structure, comprising: a silicon nitride liner that covers sidewall surfaces of the fill structure; silicon oxide on the silicon nitride liner, wherein the silicon oxide extends into a dielectric layer below the gate structure; and an air gap in the silicon oxide", in claim 14 of Pat '989, is interpreted as the same limitation).
Pat '989 does not explicitly disclose a dielectric layer surrounding the plurality of fin structures, the gate structure, and the fill structure.
Tsai teaches, in at least figure 12 and related text, the device comprising a dielectric layer (106, [16]) surrounding the plurality of fin structures (104, [12]), the gate structure (112, [12]), and the fill structure (114, [13]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Pat '989 and Tsai are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '989 with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '989 to have the dielectric layer surrounding the plurality of fin structures, the gate structure, and the fill structure, as taught by Tsai, for the purpose of providing semiconductor devices having a cut metal gate ([11, Tsai]) thereby improving density of integration.
Regarding claim 2, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 further discloses, in claim 14, the fill structure extends into the dielectric layer ("the silicon oxide extends into a dielectric layer below the gate structure", in claim 14 of Pat ‘989, is interpreted as the same limitation).
Regarding claim 3, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 2 as described above.
Pat ‘989 further discloses, in claim 20, the fill structure extends between about 50 nm and about 100 nm below an interface between the dielectric layer and a bottom surface of the gate structure ("the fill structure extends about 50 nm to about 100 nm into the dielectric layer below the gate structure ", in claim 20 of Pat ‘989, is interpreted as the same limitation).
Regarding claim 4, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the silicon nitride liner is about 5 nm thick.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of the silicon nitride liner as claimed in claim 4 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the silicon nitride liner as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the silicon nitride liner is about 5 nm thick) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 9, Pat ‘989 discloses, in claim 8, the fill structure comprises: a liner layer; a fill layer formed on the liner layer; and an air gap formed within the fill layer; and an interlayer dielectric layer surrounding the gate structure, and the fill structure ("a fill structure of substantially constant width interposed between, and substantially parallel to, adjacent fin structures of the first and second fin structures and comprising: a nitride liner on the first and second end portions; an oxide fill comprising a seam, wherein a bottom surface of the oxide fill is below bottom surfaces of the first and second gate structures; and an air gap within the oxide fill; and an interlayer dielectric material surrounding the first gate structure, the second gate structure, and the fill structure", in claim 8 of Pat '989, is interpreted as the same limitation).
Pat '989 does not explicitly disclose a plurality of field effect transistors (finFETs) with a common gate structure; a fill structure formed within the gate structure and disposed between adjacent finFETs of the plurality of finFETs; an interlayer dielectric layer surrounding the plurality of finFETs.
Tsai teaches, in at least figures 1A, 1B, and related text, the device comprising a plurality of field effect transistors (finFETs) (finfets of 104, [13]) with a common gate structure (112, [13]); a fill structure (114, [13]) formed within the gate structure (112, [13]) and disposed between adjacent finFETs of the plurality of finFETs (finfets of 104, [13]); an interlayer dielectric layer (106, [16]) surrounding the plurality of finFETs (finfets of 104, [13]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Pat '989 and Tsai are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '989 with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '989 to have the plurality of field effect transistors (finFETs) with a common gate structure; a fill structure formed within the gate structure and disposed between adjacent finFETs of the plurality of finFETs; the interlayer dielectric layer surrounding the plurality of finFETs, as taught by Tsai, for the purpose of providing semiconductor devices having a cut metal gate ([11, Tsai]) thereby improving density of integration.
Regarding claim 10, Pat ‘989 in view of Tsai discloses the structure of claim 9 as described above.
Tsai further teaches, in at least figures 1A, 1B, and related text, a bottom surface of the fill structure (114, [13]) is below an interface between the interlayer dielectric layer (106, [16]) and a bottom surface of the gate structure (112, [13]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Regarding claim 11, Pat ‘989 in view of Tsai discloses the structure of claim 9 as described above.
Pat ‘989 further discloses, in claim 11, a ratio of a liner thickness to fill layer thickness is in a range of about 1:5 to about 1:9 ("a thickness ratio of the nitride liner to the oxide fill is between about 1:5 and about 1:9", in claim 11 of Pat ‘989, is interpreted as the same limitation).
Regarding claim 12, Pat ‘989 in view of Tsai discloses the structure of claim 9 as described above.
Pat ‘989 further discloses, in claim 12, the air gap has a width less than 3 nm in a direction parallel to a width of the gate structure (all limitations are the same with the limitations recited in claim 12 of Pat 989).
Regarding claim 14, Pat ‘989 in view of Tsai discloses the structure of claim 9 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the liner layer comprises a nitrogen containing material and the fill layer comprises an oxide-based material.
Pat ‘989 teaches, in claim 14, the liner layer comprises a nitrogen containing material and the fill layer comprises an oxide-based material ("a silicon nitride liner that covers sidewall surfaces of the fill structure; silicon oxide on the silicon nitride liner, wherein the silicon oxide extends into a dielectric layer below the gate structure", in claim 14 of Pat ‘989, is interpreted as the same limitation), for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 8 of Pat ‘989 to have the liner layer comprising a nitrogen containing material and the fill layer comprises an oxide-based material, as taught by claim 14 of Pat ‘989, for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Regarding claim 17, Pat ‘989 discloses, in claim 14, a semiconductor structure, comprising:
a plurality of fin structures on a substrate; a gate structure that wraps around each fin structure of the plurality of fin structures; and a multi-layer dielectric stack formed within the gate structure and that divides the gate structure in two portions, the multi-layer dielectric stack comprising: a liner layer; a fill layer; and an air gap within the fill layer ("fin structures disposed on a substrate; a gate structure on the fin structures; and a fill structure between adjacent fin structures, wherein the fill structure divides the gate structure into sections spaced apart by the fill structure, comprising: a silicon nitride liner that covers sidewall surfaces of the fill structure; silicon oxide on the silicon nitride liner, wherein the silicon oxide extends into a dielectric layer below the gate structure; and an air gap in the silicon oxide", in claim 14 of Pat '989, is interpreted as the same limitation).
Pat '989 does not explicitly disclose a metal gate structure that wraps around each fin structure of the plurality of fin structures.
Tsai teaches, in at least figures 1A, 1B, and related text, the device comprising a metal gate structure (112, [13], [18]) that wraps around each fin structure of the plurality of fin structures (104, [13]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Pat '989 and Tsai are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '989 with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '989 to have the metal gate structure that wraps around each fin structure of the plurality of fin structures, as taught by Tsai, for the purpose of providing semiconductor devices having a cut metal gate ([11, Tsai]) thereby improving density of integration.
Regarding claim 19, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 17 as described above.
Pat ‘989 further discloses, in claim 14, the multi-layer dielectric stack comprises one or more of a silicon nitride, a silicon oxide, and a silicon oxy-carbide layer ("a silicon nitride liner that covers sidewall surfaces of the fill structure; silicon oxide on the silicon nitride liner", in claim 14 of Pat ‘989, is interpreted as the same limitation).
Claims 5, 15 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 and 14 of U.S. Patent No. 12,020,989 in view of Tsai (US 2019/0067277), and further in view of Chang (US 2017/0229451).
Regarding claim 5, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the silicon oxide fill layer comprises another air gap.
Chang teaches, in at least figure 2I and related text, the device comprising the silicon oxide fill layer (218, [24]) comprises another air gap (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989, Tsai, and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Tsai with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the silicon oxide fill layer comprising another air gap, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Regarding claim 15, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 9 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill layer comprises two additional air gaps.
Chang teaches, in at least figure 2I and related text, the device comprising the fill layer (218, [24]) comprises two additional air gaps (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989, Tsai, and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Tsai with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill layer comprising two additional air gaps, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Regarding claim 20, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 17 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill layer comprises a first additional air gap and a second additional air gap.
Chang teaches, in at least figure 2I and related text, the device comprising the fill layer (218, [24]) comprises a first additional air gap (219, [24]) and a second additional air gap (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989, Tsai, and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Tsai with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill layer comprising a first additional air gap and a second additional air gap, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Claims 6-8, 13 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 12, 14 and 20 of U.S. Patent No. 12,020,989 in view of Tsai (US 2019/0067277), and further in view of claims 1 and 6 of U.S. Patent No. 12,009,266.
Regarding claim 6, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure.
Pat ‘266 teaches, in claims 1 and 6, the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure ("depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and depositing a silicon oxide fill layer in the opening and on the silicon nitride liner" and “forming the opening comprises forming the opening with sidewalls having a negative slope along a plane parallel to a width of the gate structure”, in claim 1 and 6 of Pat ‘266, are interpreted as the same limitation), for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure, as taught by Pat ‘266, for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Regarding claim 7, Pat ‘989 in view of Tsai and Pat ‘266 discloses the semiconductor structure of claim 6 as described above.
Pat ‘989 further discloses, in claim 12, the air gap has a width less than 3 nm in a direction parallel to the width of the gate structure (all limitations are the same with the limitations recited in claim 12 of Pat 989).
Regarding claim 8, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill structure has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate.
Pat ‘266 teaches, in claim 1, the fill structure has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate ("forming an opening of substantially constant width in the gate structure between two adjacent fin structures, to divide the gate structure into first and second sections spaced apart by the opening, wherein the opening has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate; depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and depositing a silicon oxide fill layer in the opening and on the silicon nitride liner”, in claim 1 of Pat ‘266, is interpreted as the same limitation), for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill structure having a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate, as taught by Pat ‘266, for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Regarding claim 13, Pat ‘989 in view of Tsai discloses the structure of claim 12 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure.
Pat ‘266 teaches, in claims 1 and 6, the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure ("depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and depositing a silicon oxide fill layer in the opening and on the silicon nitride liner" and “forming the opening comprises forming the opening with sidewalls having a negative slope along a plane parallel to a width of the gate structure”, in claim 1 and 6 of Pat ‘266, are interpreted as the same limitation), for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill structure has sidewalls with a negative slope along a plane parallel to a width of the gate structure, as taught by Pat ‘266, for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Regarding claim 18, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 17 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose the fill structure has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate.
Pat ‘266 teaches, in claim 1, the fill structure has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate ("forming an opening of substantially constant width in the gate structure between two adjacent fin structures, to divide the gate structure into first and second sections spaced apart by the opening, wherein the opening has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate; depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and depositing a silicon oxide fill layer in the opening and on the silicon nitride liner”, in claim 1 of Pat ‘266, is interpreted as the same limitation), for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the fill structure having a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate, as taught by Pat ‘266, for the purpose of mitigating the fringing capacitances generated by the patterned gate structures.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 of U.S. Patent No. 12,020,989 in view of Tsai (US 2019/0067277), and further in view of Liou (US 2018/0144988).
Regarding claim 16, Pat ‘989 in view of Tsai discloses the semiconductor structure of claim 9 as described above.
Pat ‘989 in view of Tsai does not explicitly disclose bottom corners of the fill structure are rounded.
Liou teaches, in at least figure 12 and related text, the device comprising bottom corners of the fill structure (60, [27]) are rounded, for the purpose of providing gate isolation structure extending towards the semiconductor substrate to cut the fin structure in the semiconductor substrate for simplifying and integrating the related manufacturing processes ([7]).
Pat ‘989, Tsai, and Liou are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Tsai with the specified features of Liou because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Tsai to have the bottom corners of the fill structure being rounded, as taught by Liou, for the purpose of providing gate isolation structure extending towards the semiconductor substrate to cut the fin structure in the semiconductor substrate for simplifying and integrating the related manufacturing processes ([7], Liou).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 9, 14-15, 17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (2019/0157387) in view of Chang (2017/0229451).
Regarding claim 1, Wu discloses, in at least figure 10A and related text, a semiconductor structure, comprising:
a plurality of fin structures (104A/104B, [21]) formed on a substrate (102, [21]);
a gate structure (106A/106B, [21]) disposed on the plurality of fin structures (104A/104B, [21]);
a fill structure (113/116, [35], [37]) within the gate structure (106A/106B, [21]) and disposed between two adjacent fin structures of the plurality of fin structures (104A/104B, [21]), the fill structure comprising:
a silicon nitride liner (116, [35]);
a silicon oxide fill layer (113, [37]) on the silicon nitride liner (116, [35]); a dielectric layer (109, [30]) surrounding the plurality of fin structures (104A/104B, [21]), the gate structure (106A/106B, [21]), and the fill structure (113/116, [35], [37]).
Pat ‘989 does not explicitly disclose an air gap within the silicon oxide fill layer.
Chang teaches, in at least figure 2I and related text, the device comprising an air gap (219, [24]) within the silicon oxide fill layer (218, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989 and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 to have the air gap within the silicon oxide fill layer, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Regarding claim 4, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Chang does not explicitly disclose the silicon nitride liner is about 5 nm thick.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of the silicon nitride liner as claimed in claim 4 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the silicon nitride liner as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the silicon nitride liner is about 5 nm thick) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 5, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 1 as described above.
Chang further teaches, in at least figure 2I and related text, the silicon oxide fill layer (218, [24]) comprises another air gap (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Regarding claim 9, Wu discloses, in at least figures 3, 10A, and related text, a structure, comprising:
a plurality of field effect transistors (finFETs) (finfets of 104A/104B, [20], [21]) with a common gate structure (106A/106B, [21]); and
a fill structure (113/116, [35], [37]) formed within the gate structure (106A/106B, [21]) and disposed between adjacent finFETs of the plurality of finFETs (finfets of 104A/104B, [20], [21]), wherein the fill structure (113/116, [35], [37]) comprises:
a liner layer (116, [35]);
a fill layer (113, [37]) formed on the liner layer (116, [35]); and
an interlayer dielectric layer (109, [30]) surrounding the plurality of finFETs (finfets of 104A/104B, [20], [21]), the gate structure (106A/106B, [21]), and the fill structure (113/116, [35], [37]).
Pat ‘989 does not explicitly disclose an air gap formed within the fill layer.
Chang teaches, in at least figure 2I and related text, the device comprising an air gap (219, [24]) formed within the fill layer (218, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989 and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 to have the air gap formed within the fill layer, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Regarding claim 14, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 9 as described above.
Wu further discloses, in at least figures 3, 10A, and related text, the liner layer (116, [35]) comprises a nitrogen containing material and the fill layer (113, [37]) comprises an oxide-based material.
Regarding claim 15, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 9 as described above.
Chang further teaches, in at least figure 2I and related text, the fill layer (218, [24]) comprises two additional air gaps (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Regarding claim 17, Wu discloses, in at least figures 3, 10A, and related text, a semiconductor structure, comprising:
a plurality of fin structures (104A/104B, [21]) on a substrate (102, [21]);
a metal gate structure (106A/106B, [21]) that wraps around each fin structure of the plurality of fin structures (104A/104B, [21]); and
a multi-layer dielectric stack (113/116, [35], [37]) formed within the metal gate structure (106A/106B, [21]) and that divides the metal gate structure (106A/106B, [21]) in two portions, the multi-layer dielectric stack (113/116, [35], [37]) comprising:
a liner layer (116, [35]);
a fill layer (113, [37]).
Pat ‘989 does not explicitly disclose an air gap within the fill layer.
Chang teaches, in at least figure 2I and related text, the device comprising an air gap (219, [24]) within the fill layer (218, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Pat ‘989 and Chang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 with the specified features of Chang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 to have the air gap within the fill layer, as taught by Chang, for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31], Chang).
Regarding claim 19, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 17 as described above.
Wu further discloses, in at least figures 3, 10A, and related text, the multi-layer dielectric stack (113/116, [35], [37]) comprises one or more of a silicon nitride (116, [35]), a silicon oxide (113, [37]), and a silicon oxy-carbide layer.
Regarding claim 20, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 17 as described above.
Chang further teaches, in at least figure 2I and related text, the fill layer (218, [24]) comprises a first additional air gap (219, [24]) and a second additional air gap (219, [24]), for the purpose of preventing line-end bridge defect and leakage and enhancing yield and reliability of the FinFET ([31]).
Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (2019/0157387) in view of Chang (2017/0229451), and further in view of Tsai (US 2019/0067277).
Regarding claim 2, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 1 as described above.
Pat ‘989 in view of Chang does not explicitly disclose the fill structure extends into the dielectric layer.
Tsai teaches, in at least figures 1A, 1B, and related text, the device comprising the fill structure (114, [13]) extends into the dielectric layer (106, [16]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Pat ‘989, Chang, and Tsai are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Chang with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Chang to have the fill structure extending into the dielectric layer, as taught by Tsai, for the purpose of providing semiconductor devices having a cut metal gate ([11], Tsai) thereby improving density of integration.
Regarding claim 10, Pat ‘989 in view of Chang discloses the structure of claim 9 as described above.
Pat ‘989 in view of Chang does not explicitly disclose a bottom surface of the fill structure is below an interface between the interlayer dielectric layer and a bottom surface of the gate structure.
Tsai teaches, in at least figures 1A, 1B, and related text, the device comprising a bottom surface of the fill structure (114, [13]) is below an interface between the interlayer dielectric layer (106, [16]) and a bottom surface of the gate structure (112, [13]), for the purpose of providing semiconductor devices having a cut metal gate ([11]) thereby improving density of integration.
Pat ‘989, Chang, and Tsai are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Chang with the specified features of Tsai because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Chang to have the bottom surface of the fill structure being below an interface between the interlayer dielectric layer and a bottom surface of the gate structure, as taught by Tsai, for the purpose of providing semiconductor devices having a cut metal gate ([11], Tsai) thereby improving density of integration.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (2019/0157387) in view of Chang (2017/0229451), and further in view of Liou (US 2018/0144988).
Regarding claim 16, Pat ‘989 in view of Chang discloses the semiconductor structure of claim 9 as described above.
Pat ‘989 in view of Chang does not explicitly disclose bottom corners of the fill structure are rounded.
Liou teaches, in at least figure 12 and related text, the device comprising bottom corners of the fill structure (60, [27]) are rounded, for the purpose of providing gate isolation structure extending towards the semiconductor substrate to cut the fin structure in the semiconductor substrate for simplifying and integrating the related manufacturing processes ([7]).
Pat ‘989, Chang, and Liou are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat ‘989 in view of Chang with the specified features of Liou because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat ‘989 in view of Chang to have the bottom corners of the fill structure being rounded, as taught by Liou, for the purpose of providing gate isolation structure extending towards the semiconductor substrate to cut the fin structure in the semiconductor substrate for simplifying and integrating the related manufacturing processes ([7], Liou).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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