Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This office action is in response to the filing with the office dated 05/20/2024.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 07/04/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
4. Claims 13-15 are rejected under 35 U.S.C. 112(b) as being indefinite for claiming two statutory categories of invention in a single claim recitation. A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite. Ex parte Lyell, 17 USPQ2d 1548 (Bd. Pat. App. & Inter. 1990). Such a claim is directed to neither a “process” nor a “machine,” but rather embraces or overlaps two different statutory classes of invention. MPEP § 2173.05(p).
Claim 13 recites “A method of using a test element group comprising, providing the test element group according to claim 1, providing a first photomask to form……………”.
Claim 1 already recites first, second and third probe pads, upper row contacting region and lower row contacting region. The vias recited as part of the method of claim 13, using test element group of claim 1 would have been already formed. It is confusing how an already formed pad structure (test element group of claim 1) which has vias in the layers beneath the pad structure would need a photomask to form the vias.
Claim 14 recites “providing a second photomask to seal the three of the plurality of vias in the at least one upper row contacting region, and to form three of….”. similar rational for this rejection is applied as for claim 13.
Claims 1 is rejected due to their dependency on claim 13.
Appropriate clarification and correction to the claim language is required. Applicant is advised to rewrite the method claim as independent claim with process flow steps to avoid confusion currently present in the recitation of claims 13-15.
Claim Rejections – 35 U.S.C. 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hess et al (US 2007/0075718 A1).
Examiner Note: Hess et al (US 2007/0075718 A1) teaches the claimed invention as multiple exemplary embodiments. Hence claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hess et al (US 2007/0075718 A1).
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Regarding independent claim 1, Hess et al (US 20070075718 A1) teaches, A test element group located at a scribe line of a wafer (figure1), the test element group comprising: a first probe pad; at least one second probe pad; at least one third probe pad (pad set 104, paragraph [0026] gate force pad 108, source pad 110, and drain pad 112); the first probe pad, the at least one second probe pad, and the at least one third probe pad sequentially aligned (figure 2-B); at least one upper row contacting region located between the at least one second probe pad and the at least one third probe pad; and at least one lower row contacting region opposite to the at least one upper row contacting region, the at least one lower row contacting region located between the at least one second probe pad and the at least one third probe pad (As also depicted in FIG. 2-B, any number of metal layers 202 can be formed between the layers in which DUT array 102 and pad array 104 are formed to interconnect the DUTs in DUT array 102 and gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 in pad array 104, paragraph [0029], figures 6-11, paragraphs [0039]-[0044]); wherein when the at least one upper row contacting region is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one lower row contacting region is insulated from the first probe pad, the at least one second probe pad, and the at least one third probe pad ([0033] FIG. 4 depicts an individual DUT 402 connected to source pad 110, drain
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pad 112, gate force pad 108, and gate sense pad 106. For the sake of example, DUT 402 is depicted as an NMOS transistor. It should be recognized, however, that DUT 402 can be various types of devices. [0034] FIG. 4 depicts the source and drain of DUT 402 connected to source pad 110 and drain pad 112, respectively, through tree-routed structures, which will be described in greater detail below. In the present exemplary embodiment, the sources of all the DUTs in a particular DUT array are connected in parallel to source pad 110 through a source tree routing structure, which will be described in greater detail below. Additionally, the drains of all the DUTs in a particular DUT array are connected in parallel to drain pad 112 through a drain tree routing structure, which will be described in greater detail below. Thus, during electrical testing, probes in contact with source pad 110 and drain pad 112 can send and receive signals to and from all the DUTs in a DUT array at one time in parallel. [0035] FIG. 4 also depicts the gate of DUT 402 connected to gate force pad 108 and gate sense pad 106 through a selection circuit 400. In the present exemplary embodiment, the gates of all the DUTs in a particular DUT array are connected to gate force pad 108 and gate sense pad 106 through selection circuit 400. Thus, during electrical testing, probes in contact with gate force pad 108 and gate sense pad 106 are connected to one DUT in a DUT array at a time through selection circuit 400. Each DUT in the DUT array is then selected for testing. As noted above, the gate sense pad 106 can be eliminated in some applications, such as when the gate leakage is negligible.[0036] To test each DUT in a DUT array, selection circuit 400 is used to select each DUT addressed by row and column selection signals); or wherein when the at least one lower row contacting region is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the at least one upper row contacting region is insulated from the first probe pad, the at least one second probe pad, and
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the at least one third probe pad ([0033] FIG. 4 depicts an individual DUT 402 connected to source pad 110, drain pad 112, gate force pad 108, and gate sense pad 106. For the sake of example, DUT 402 is depicted as an NMOS transistor. It should be recognized, however, that DUT 402 can be various types of devices. [0034] FIG. 4 depicts the source and drain of DUT 402 connected to source pad 110 and drain pad 112, respectively, through tree-routed structures, which will be described in greater detail below. In the present exemplary embodiment, the sources of all the DUTs in a particular DUT array are connected in parallel to source pad 110 through a source tree routing structure, which will be described in greater detail below. Additionally, the drains of all the DUTs in a particular DUT array are connected in parallel to drain pad 112 through a drain tree routing structure, which will be described in greater detail below. Thus, during electrical testing, probes in contact with source pad 110 and drain pad 112 can send and receive signals to and from all
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the DUTs in a DUT array at one time in parallel. [0035] FIG. 4 also depicts the gate of DUT 402 connected to gate force pad 108 and gate sense pad 106 through a selection circuit 400. In the present exemplary embodiment, the gates of all the DUTs in a particular DUT array are connected to gate force pad 108
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and gate sense pad 106 through selection circuit 400. Thus, during electrical testing, probes in contact with gate force pad 108 and gate sense pad 106 are connected to one DUT in a DUT array at a
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time through selection circuit 400. Each DUT in the DUT array is then selected for testing. As noted above, the gate sense pad 106 can be eliminated in some applications, such as when the gate leakage is negligible.[0036] To test each DUT in a DUT array, selection circuit 400 is used to select each DUT addressed by row and column selection signals). It is inherent that each of these layers are insulated from each other to prevent shorting and also selection circuit 400 to selectively contact and test each DUT).
Regarding dependent claim 2, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
Hess et al further teaches, wherein the at least one upper row contacting region comprises three of a plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2B, paragraph [0029] As also depicted in FIG. 2-B, any number of metal layers 202 can be formed between the layers in which DUT array 102 and pad array 104 are formed to interconnect the DUTs in DUT array 102 and gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 in pad array 104; Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 3, Hess et al (US 20070075718 A1) teaches the test element group of claim 2.
Hess et al further teaches, wherein when the at least one upper row contacting region is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the three of the plurality of vias electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2B, paragraph [0029] As also depicted in FIG. 2-B, any number of metal layers 202 can be formed between the layers in which DUT array 102 and pad array 104 are formed to interconnect the DUTs in DUT array 102 and gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 in pad array 104; Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 4, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
Hess et al further teaches, wherein the at least one lower row contacting region comprises three of a plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2B, paragraph [0029] As also depicted in FIG. 2-B, any number of metal layers 202 can be formed between the layers in which DUT array 102 and pad array 104 are formed to interconnect the DUTs in DUT array 102 and gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 in pad array 104; [0033] FIG. 4 depicts an individual DUT 402 connected to source pad 110, drain pad 112, gate force pad 108, and gate sense pad 106. For the sake of example, DUT 402 is depicted as an NMOS transistor. It should be recognized, however, that DUT 402 can be various types of devices. [0034] FIG. 4 depicts the source and drain of DUT 402 connected to source pad 110 and drain pad 112, respectively, through tree-routed structures, which will be described in greater detail below. In the present exemplary embodiment, the sources of all the DUTs in a particular DUT array are connected in parallel to source pad 110 through a source tree routing structure, which will be described in greater detail below. Additionally, the drains of all the DUTs in a particular DUT array are connected in parallel to drain pad 112 through a drain tree routing structure, which will be described in greater detail below. Thus, during electrical testing, probes in contact with source pad 110 and drain pad 112 can send and receive signals to and from all the DUTs in a DUT array at one time in parallel; [0035] FIG. 4 also depicts the gate of DUT 402 connected to gate force pad 108 and gate sense pad 106 through a selection circuit 400. In the present exemplary embodiment, the gates of all the DUTs in a particular DUT array are connected to gate force pad 108 and gate sense pad 106 through selection circuit 400. Thus, during electrical testing, probes in contact with gate force pad 108 and gate sense pad 106 are connected to one DUT in a DUT array at a time through selection circuit 400. Each DUT in the DUT array is then selected for testing. As noted above, the gate sense pad 106 can be eliminated in some applications, such as when the gate leakage is negligible. [0036] To test each DUT in a DUT array, selection circuit 400 is used to select each DUT addressed by row and column selection signals. Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 5, Hess et al (US 20070075718 A1) teaches the test element group of claim 4.
Hess et al further teaches, wherein when the at least one lower row contacting region is electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, the three of the plurality of vias electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figures 3 and 4, selection circuit [0035] FIG. 4 also depicts the gate of DUT 402 connected to gate force pad 108 and gate sense pad 106 through a selection circuit 400. In the present exemplary embodiment, the gates of all the DUTs in a particular DUT array are connected to gate force pad 108 and gate sense pad 106 through selection circuit 400. Thus, during electrical testing, probes in contact with gate force pad 108 and gate sense pad 106 are connected to one DUT in a DUT array at a time through selection circuit 400. Each DUT in the DUT array is then selected for testing. As noted above, the gate sense pad 106 can be eliminated in some applications, such as when the gate leakage is negligible. [0036] To test each DUT in a DUT array, selection circuit 400 is used to select each DUT addressed by row and column selection signals. Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 6, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
Hess et al further teaches,, wherein a number of the at least one second probe pad is two second probe pads; a number of the at least one third probe pad is two third probe pads; each one of the two second probe pads and each one of the two third probe pads are arranged interactively in sequence (Multiple layers of pads and DUTs are taught Figures 2B, 4, 6 paragraphs [0039]-[0043])
Regarding dependent claim 7, Hess et al (US 20070075718 A1) teaches the test element group of claim 6.
Hess et al further teaches, wherein a number of the at least one upper row contacting region is three upper row contacting regions (figures 2-B, 3-6, 10, 11, paragraphs [0026]-[0028]); and a number of the at least one lower row contacting region is three lower row contacting regions (figure 2-B, paragraphs [0029], [0033], [0035]); wherein each one of the three upper row contacting regions is located between adjacent one of the two second probe pads and adjacent one of the two third probe pads, wherein each one of the three lower row contacting regions is located between adjacent one of the two second probe pads and adjacent one of the two third probe pads (Figure 2B [0026] Layout 100 also includes a pad set 104 formed adjacent to DUT array 102. In particular, in the present exemplary embodiment, pad set 104 includes a gate sense pad 106, a gate force pad 108, a source pad 110, and a drain pad 112. Each DUT in DUT array 102 is connected to gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 of pad set 104. As described in greater detail below, layout 100 can be formed without gate sense pad 106. Thus, pad set 104 can include only gate force pad 108, source pad 110, and drain pad 112. [0028] After layout 100 has been formed, each DUT in DUT array 102 is electrically tested on the wafer using a wafer tester. In particular, in the present exemplary embodiment, probes on the wafer tester contact gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112, then test each DUT in DUT array 102 individually in series. As noted above, layout 100 can be formed without gate sense pad 106, in which case, probes on the wafer tester contact gate force pad 108, source pad 110, and drain pad 112, then test each DUT in DUT array 102 individually in series. In the present exemplary embodiment, the DUTs in DUT array 102 are sequentially tested. It should be recognized, however, that the DUTs in DUT array 102 can be tested individually in series in any desired order. Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 8, Hess et al (US 20070075718 A1) teaches the test element group of claim 6.
Hess et al further teaches, wherein the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one second probe pad is at least one source probe pad. Figure 2B [0026] Layout 100 also includes a pad set 104 formed adjacent to DUT array 102. In particular, in the present exemplary embodiment, pad set 104 includes a gate sense pad 106, a gate force pad 108, a source pad 110, and a drain pad 112. Each DUT in DUT array 102 is connected to gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 of pad set 104. As described in greater detail below, layout 100 can be formed without gate sense pad 106. Thus, pad set 104 can include only gate force pad 108, source pad 110, and drain pad 112.
Regarding dependent claim 9, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
Hess et al further teaches, wherein a width of the test element group is less than or equal to a width of scribe line being from 50 μm to 60 μm (figure 3, paragraph [0049]).
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Regarding dependent claim 10, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
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Hess et al further teaches, wherein the test element group further comprises: a substrate; a plurality of metal layers over the substrate (figures 2-B and 10; paragraphs [0029]-[0036]) a top layer over the plurality of metal layers, and the top layer comprising the first probe pad, the at least one second probe pad, and the at least one third probe pad (figures 2-B; paragraphs [0029]-[0036]); and a plurality of vias connected to at least one of the plurality of metal layers;
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wherein the at least one upper row contacting region comprises three of the plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (Selection circuit 400 connected to gate force pad,
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gate sense pad,
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source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding dependent claim 11, Hess et al (US 20070075718 A1) teaches the test element group of claim 10.
Hess et al further teaches, wherein the at least one lower row contacting region comprises three of the plurality of vias corresponding to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2B, paragraph [0029] As also depicted in FIG. 2-B, any number of metal layers 202 can be formed between the layers in which DUT array 102 and pad array 104 are formed to interconnect the DUTs in DUT array 102 and gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 in pad array 104).
Regarding dependent claim 12, Hess et al (US 20070075718 A1) teaches the test element group of claim 10.
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Hess et al further teaches,, wherein the plurality of metal layers comprises an active layer and a gate electrode layer over the active layer; wherein the wafer further comprises an insulating layer disposed between the active layer and the gate electrode layer (it is inherent that a semiconductor device as shown in figures 2-B, 3, 4, 6 and 10 will have an active semiconductor layer, metal interconnect structure and its connections to contact pads and gate insulation layer. It is also inherent that each of these layers are insulated from each other as needed to prevent shorting and also selection circuit 400 to selectively contact and test each DUT).
Regarding dependent claim 13, Hess et al (US 20070075718 A1) teaches the test element group of claim 1.
Hess et al further teaches A method of using a test element group, comprising: three of a plurality of vias in the at least one upper row contacting region and the three of the plurality of vias electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2-B, 3, 6, 10, 11 and paragraphs [0026]-[0028], [0034]-[0036]); and detecting an upper chip through contacting the three of the plurality of vias in the at least one upper row contacting region, the first probe pad, the at least one second probe pad, and the at least one third probe pad by a test device (Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043].
Regarding the limitation “providing the test element group of claim 1; providing a first photomask to form”, Please see the 35 U.S.C. 112 rejection above.
Regarding dependent claim 14, Hess et al (US 20070075718 A1) teaches the test element group of claim 13.
Hess et al further teaches, further comprising: a plurality of vias in the at least one lower row contacting region and the three of the plurality of vias electrically connected to the first probe pad, the at least one second probe pad, and the at least one third probe pad, respectively (figure 2-B, 3, 6, 10 and 11, paragraphs [0026]-[0028], [0034]-[0036]); and detecting a lower chip through contacting the three of the plurality of vias in the at least one lower row contacting region, the first probe pad, the at least one second probe pad, and the at least one third probe pad by the test device (Selection circuit 400 connected to gate force pad, gate sense pad, source pad and drain pad, vias or tree routing structures are also shown in figure 6, and described in paragraphs [0039]-[0043]).
Regarding the limitation “providing a second photomask to seal the three of the plurality of vias in the at least one upper row contacting region, and to form three of” Please see the 35 U.S.C. 112 rejection above.
Regarding dependent claim 15, Hess et al (US 20070075718 A1) teaches the test element group of claim 13.
Hess et al further teaches, wherein the first probe pad is a gate probe pad, the at least one second probe pad is at least one drain probe pad, and the at least one second probe pad is at least one source probe pad (Figure 2B [0026] Layout 100 also includes a pad set 104 formed adjacent to DUT array 102. In particular, in the present exemplary embodiment, pad set 104 includes a gate sense pad 106, a gate force pad 108, a source pad 110, and a drain pad 112. Each DUT in DUT array 102 is connected to gate sense pad 106, gate force pad 108, source pad 110, and drain pad 112 of pad set 104. As described in greater detail below, layout 100 can be formed without gate sense pad 106. Thus, pad set 104 can include only gate force pad 108, source pad 110, and drain pad 112).
Closest Prior art
6. The following relevant prior art of record is not cited in the office action.
Ma (US 2011/0050273 A1) teaches, A fast testable wafer includes a die group, testing points located on dies, a scribe line located between the dies, and a plurality of testing pads disposed in the scribe line area. The testing points comprise bonding pads or electrodes of internal circuits within the dies. The testing pads and bonding pads may be electrically connected and arranged suitably such that testing probes may be electrically connected to the testing pads and bonding pads easily so as to test the plurality of dies at about the same time. Through suitable circuits on the wafer, different circuit routes may be selected to connect the testing pads and different testing points on the dies so as to test a plurality of dies without moving the testing probes and thereby accelerating the test.
Killingsworth (US 2015/0287655 A1) Teaches, A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURESH RAJAPUTRA whose telephone number is (571) 270-0477. The examiner can normally be reached between 8:00 AM - 5:00 PM.
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/SURESH RAJAPUTRA/
Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 2/23/2026