CTNF 18/668,706 CTNF 98228 DETAILED ACTION This Office action responds to Applicant’s invention filed on 05/20/2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis ( i.e. , changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20. Information Disclosure Statement (IDS) Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDSs have been considered. Specification Objection 06-31 AIA The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814 CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 13 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite. The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claims 13 and 20 (and any dependents) recites the limitation " first fingers of first capacitor plates of at least some of the additional capacitors are offset vertically and second fingers of second capacitor plates of at least some of the additional capacitors are offset vertically”. It is not clear what is the reference with respect to the vertical offset occurs. For the purpose of the prosecution, Examiner considers that this reference is the dielectric layer above the transistor. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-2, 6-8, 12, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 2008/0230820) in view of Soussan (FR 2982707) . Regarding claim 1, Maeda shows (see, e.g. , Maeda: figs. 2-4, and 6-10) most aspects of the instant invention including a structure, comprising: A first capacitor C1 including a transistor, wherein the transistor includes: A channel region 4 in a semiconductor layer 3/1 positioned laterally between source/drain regions 7 A front gate 6 adjacent to a top surface of the semiconductor layer 3/1 at the channel region 4 wherein: The source/drain regions 7 are connected to a first terminal 12a/M1a (see, e.g. , Maeda: fig. 3) The front gate 6 is connected to a second terminal 12b/M1b (see, e.g. , Maeda: fig. 4) A dielectric layer 11 on the transistor An additional capacitor MP1/MP2 above the dielectric layer 11 extending at least partially over the front gate 6 wherein: the additional capacitor MP1/MP2 includes interdigitated capacitor plates connected to the first terminal 12a/M1a and the second terminal 12b/M1b , respectively However, Maeda fails (see, e.g. , Maeda: figs. 2-4, and 6-10) to show a back gate adjacent to a bottom surface of the semiconductor layer 3/1 at the channel region 4 . Soussan, in a similar device to Maeda, shows (see, e.g. , Soussan: figs. 2A-2B) a back gate 35 adjacent to a bottom surface of the semiconductor layer S/I/D at the channel region I . Soussan also shows (see, e.g. , Soussan: figs. 2A-2B) that the back gate 35 is connected with a well tap 32 . Furthermore, Soussan shows that the back gate contributes to reducing the access resistance to the capacitance Cl of the transistor (see, e.g. , Soussan: par. [0004]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the back gate of Soussan in the device of Maeda in order to reduce the access resistance to the capacitance of the transistor, and increasing the capacitance of the transistor. Regarding claim 2, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B): A semiconductor substrate 21 An insulator layer 22 on the semiconductor substrate 21 wherein: the bottom surface of the semiconductor layer S/I/D is immediately adjacent to the insulator layer 22 a well region 35 in the semiconductor substrate 21 immediately adjacent to the insulator layer 22 and below the transistor wherein: Portions of the insulator layer 22 and the well region 35 adjacent to the channel region I opposite the front gate G form the back gate 35 Regarding claim 6, Maeda in view of Soussan shows (see, e.g. , Maeda: figs. 2-4, and 6-10) that: The interdigitated capacitor plates MP1/MP2 include a first capacitor plate MP1 with first fingers MD1 and a second capacitor plate MP2 with second fingers MD2 At least some of the first fingers MD1 extend at least partially across the front gate 6 in one direction At least some of the second fingers MD2 extend at least partially across the front gate 6 in an opposite direction Regarding claim 7, Maeda shows (see, e.g. , Maeda: figs. 2-4, and 6-10) most aspects of the instant invention including a structure, comprising: A first capacitor C1 including a transistor, wherein the transistor includes: A channel region 4 in a semiconductor layer 3/1 positioned laterally between source/drain regions 7 A front gate 6 adjacent to a top surface of the semiconductor layer 3/1 at the channel region 4 wherein: The source/drain regions 7 are connected to a first terminal 12a/M1a (see, e.g. , Maeda: fig. 3) The front gate 6 is connected to a second terminal 12b/M1b (see, e.g. , Maeda: fig. 4) A dielectric layer 11 on the transistor An additional capacitor MP1/MP2 above the dielectric layer 11 extending at least partially over the front gate 6 wherein: the additional capacitor MP1/MP2 includes interdigitated capacitor plates connected to the first terminal 12a/M1a and the second terminal 12b/M1b , respectively However, Maeda fails (see, e.g. , Maeda: figs. 2-4, and 6-10) to show a back gate adjacent to a bottom surface of the semiconductor layer 3/1 at the channel region 4 . Soussan, in a similar device to Maeda, shows (see, e.g. , Soussan: figs. 2A-2B) a back gate 35 adjacent to a bottom surface of the semiconductor layer S/I/D at the channel region I . Soussan also shows (see, e.g. , Soussan: figs. 2A-2B) that the back gate 35 is connected with a well tap 32 . Furthermore, Soussan shows that the back gate contributes to reducing the access resistance to the capacitance Cl of the transistor (see, e.g. , Soussan: par. [0004]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the back gate of Soussan in the device of Maeda in order to reduce the access resistance to the capacitance of the transistor, and increasing the capacitance of the transistor. Regarding claim 8, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B): A semiconductor substrate 21 An insulator layer 22 on the semiconductor substrate 21 wherein: the bottom surface of the semiconductor layer S/I/D is immediately adjacent to the insulator layer 22 a well region 35 in the semiconductor substrate 21 immediately adjacent to the insulator layer 22 and below the transistor wherein: Portions of the insulator layer 22 and the well region 35 adjacent to the channel region I opposite the front gate G form the back gate 35 Regarding claim 12, Maeda in view of Soussan shows (see, e.g. , Maeda: figs. 2-4, and 6-10) that: The interdigitated capacitor plates MP1/MP2 include a first capacitor plate MP1 with first fingers MD1 and a second capacitor plate MP2 with second fingers MD2 At least some of the first fingers MD1 extend at least partially across the front gate 6 in one direction At least some of the second fingers MD2 extend at least partially across the front gate 6 in an opposite direction Regarding claim 16, Maeda shows (see, e.g. , Maeda: figs. 2-4, and 6-10) most aspects of the instant invention including a method, comprising: Forming a first capacitor C1 including a transistor, wherein the transistor includes: A channel region 4 in a semiconductor layer 3/1 positioned laterally between source/drain regions 7 A front gate 6 adjacent to a top surface of the semiconductor layer 3/1 at the channel region 4 wherein: The source/drain regions 7 are connected to a first terminal 12a/M1a (see, e.g. , Maeda: fig. 3) The front gate 6 is connected to a second terminal 12b/M1b (see, e.g. , Maeda: fig. 4) Forming a dielectric layer 11 on the transistor Forming at least one additional capacitor MP1/MP2 above the dielectric layer 11 extending at least partially over the front gate 6 wherein: The additional capacitor MP1/MP2 includes interdigitated capacitor plates connected to the first terminal 12a/M1a and the second terminal 12b/M1b , respectively However, Maeda fails (see, e.g. , Maeda: figs. 2-4, and 6-10) to show a back gate adjacent to a bottom surface of the semiconductor layer 3/1 at the channel region 4 . Soussan, in a similar method to Maeda, shows (see, e.g. , Soussan: figs. 2A-2B) a back gate 35 adjacent to a bottom surface of the semiconductor layer S/I/D at the channel region I . Soussan also shows (see, e.g. , Soussan: figs. 2A-2B) that the back gate 35 is connected with a well tap 32 . Furthermore, Soussan shows that the back gate contributes to reducing the access resistance to the capacitance Cl of the transistor (see, e.g. , Soussan: par. [0004]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the back gate of Soussan in the method of Maeda in order to reduce the access resistance to the capacitance of the transistor, and increasing the capacitance of the transistor. Regarding claim 17, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B): Providing a semiconductor-on-insulator structure including: A semiconductor substrate 21 An insulator layer 22 on the semiconductor substrate 21 The semiconductor layer S/I/D on the insulator layer 22 Forming a well region 35 in the semiconductor substrate 21 immediately adjacent to the insulator layer 22 wherein: Portions of the insulator layer 22 and the well region 35 form the back gate 35 Regarding claim 19, Maeda in view of Soussan shows (see, e.g. , Maeda: figs. 2-4, and 6-10) the forming of at least one additional capacitor including forming that: The interdigitated capacitor plates MP1/MP2 of each additional capacitor A first capacitor plate MP1 with first fingers MD1 extending at least partially across the front gate 6 in one direction A first capacitor plate MP2 with second fingers MD2 extend at least partially across the front gate 6 in an opposite direction Regarding claim 20, Maeda in view of Soussan in view of Jain shows (see, e.g. , Maeda: figs. 2-4, and 6-10) forming of at least one additional capacitor including: Forming a stack of additional capacitors, wherein, within the stack: First fingers MD1 of first capacitor plates MP1 of at least some of the additional capacitors are offset vertically (for example, interdigitated capacitor plates MP1/MP4 for a capacitor MP1/MP4 where the capacitor plates are offset vertically) Second fingers MD4 of the second capacitor plates MP4 of at least some of the additional capacitors are offset vertically (for example, interdigitated capacitor plates MP1/MP4 for a capacitor MP1/MP4 where the capacitor plates are offset vertically) 07-21-aia AIA Claim s 3-4, 9-10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda in view of Soussan in further view of Mishra (US 2025/0328159) . Regarding claim 3, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: The semiconductor substrate 21 has P-type conductivity The total capacitance provided by the first capacitor includes at least a front gate capacitance Cgs/Cgi/Cgd and a back gate capacitance C1 (see, e.g. , Soussan: figs. 2C). However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well region has N-type conductivity. Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that the well region has P-type conductivity. Mishra, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Mishra: fig. 5) that the well region 505 has N-type concutivity (see, e.g. , Mishra: par. [0067]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the N-type well region of Mishra or P-type well region of Maeda in view of Soussan because these were recognized in the semiconductor art for their use as wells for the back gates in transistors, as taught by Mishra and by Maeda in view of Soussan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc. , 550 U.S.--,82 USPQ2d 1385 (2007). Regarding claim 4, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: The semiconductor substrate 21 is a P-type silicon substrate (see, e.g. , Soussan: par. [0004]) The semiconductor layer S/I/D is a silicon layer (see, e.g. , Soussan: par. [0004]) The transistor is a silicon-on-insulator N-type field effect transistor (see, e.g. , Soussan: par. [0002], and [0004], and fig. 2A) However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well region has N-type conductivity. Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that the well region has P-type conductivity. Mishra, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Mishra: fig. 5) that the well region 505 has N-type conductivity (see, e.g. , Mishra: par. [0067]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the N-type well region of Mishra or P-type well region of Maeda in view of Soussan because these were recognized in the semiconductor art for their use as wells for the back gates in transistors, as taught by Mishra and by Maeda in view of Soussan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc. , 550 U.S.--,82 USPQ2d 1385 (2007). Maeda in view of Soussan in view of Mishra (see, e.g. , Mishra: fig. 5) shows that the insulator layer 507 is a silicon dioxide layer (see, e.g. , Mishra: par. [0067]). Regarding claim 9, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: The semiconductor substrate 21 has P-type conductivity The total capacitance provided by the first capacitor includes at least a front gate capacitance Cgs/Cgi/Cgd and a back gate capacitance C1 (see, e.g. , Soussan: figs. 2C). However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well region has N-type conductivity. Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that the well region has P-type conductivity. Mishra, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Mishra: fig. 5) that the well region 505 has N-type concutivity (see, e.g. , Mishra: par. [0067]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the N-type well region of Mishra or P-type well region of Maeda in view of Soussan because these were recognized in the semiconductor art for their use as wells for the back gates in transistors, as taught by Mishra and by Maeda in view of Soussan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc. , 550 U.S.--,82 USPQ2d 1385 (2007). Regarding claim 10, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: The semiconductor substrate 21 is a P-type silicon substrate (see, e.g. , Soussan: par. [0004]) The semiconductor layer S/I/D is a silicon layer (see, e.g. , Soussan: par. [0004]) The transistor is a silicon-on-insulator N-type field effect transistor (see, e.g. , Soussan: par. [0002], and [0004], and fig. 2A) However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well region has N-type conductivity. Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that the well region has P-type conductivity. Mishra, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Mishra: fig. 5) that the well region 505 has N-type conductivity (see, e.g. , Mishra: par. [0067]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the N-type well region of Mishra or P-type well region of Maeda in view of Soussan because these were recognized in the semiconductor art for their use as wells for the back gates in transistors, as taught by Mishra and by Maeda in view of Soussan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc. , 550 U.S.--,82 USPQ2d 1385 (2007). Maeda in view of Soussan in view of Mishra (see, e.g. , Mishra: fig. 5) shows that the insulator layer 507 is a silicon dioxide layer (see, e.g. , Mishra: par. [0067]). Regarding claim 18, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: The semiconductor substrate 21 is a P-type silicon substrate (see, e.g. , Soussan: par. [0004]) The semiconductor layer S/I/D is a silicon layer (see, e.g. , Soussan: par. [0004]) The transistor is a silicon-on-insulator N-type field effect transistor (see, e.g. , Soussan: par. [0002], and [0004], and fig. 2A) However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well region has N-type conductivity. Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that the well region has P-type conductivity. Mishra, in a similar method to Maeda in view of Soussan, shows (see, e.g. , Mishra: fig. 5) that the well region 505 has N-type conductivity (see, e.g. , Mishra: par. [0067]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the N-type well region of Mishra or P-type well region of Maeda in view of Soussan because these were recognized in the semiconductor art for their use as wells for the back gates in transistors, as taught by Mishra and by Maeda in view of Soussan, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc. , 550 U.S.--,82 USPQ2d 1385 (2007). Maeda in view of Soussan in view of Mishra (see, e.g. , Mishra: fig. 5) shows that the insulator layer 507 is a silicon dioxide layer (see, e.g. , Mishra: par. [0067]) . 07-21-aia AIA Claim s 5, 11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda in view of Soussan in further view of Jain (US 11979145) . Regarding claim 5, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: A well tap 32 is within an opening in the insulator layer 22 The well tap 32 is adjacent the well region 35 The well tap 32 has the same type of conductivity as the well region 35 However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well tap 32 has a higher conductivity level than the well region 35 . Jain, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Jain: fig. 2B) that the well tap 218 (as P+ type, see, e.g. , Jain: col.5/I.47-54)]) has a higher conductivity level than the well region 203 (as P type, see, e.g. , Jain: col.4/I.27-34). Jain also shows (see, e.g. , Jain: fig. 2B) that the well tap 218 can be electrically isolated from the PFETs and NFETs on the same side of the deep isolation region, respectively, by shallow trench isolation (STI) regions 206 . Such well tap 218 can be contacted to facilitate biasing of the Pwells. Thus, for each FET, the Pwell and the section of insulator layer 205 below the channel region can effectively function as a gate conductor and gate dielectric and, thereby as a back gate (see, e.g. , Jain: col.5/I.50-59). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the well tap with higher conductivity level than the well region of Jain in the device of Maeda in view of Soussan in order to facilitate biasing of the wells. Regarding claim 11, Maeda in view of Soussan shows (see, e.g. , Soussan: figs. 2A-2B) that: A well tap 32 is within an opening in the insulator layer 22 The well tap 32 is adjacent the well region 35 The well tap 32 has the same type of conductivity as the well region 35 However, Maeda in view of Soussan fails (see, e.g. , Soussan: figs. 2A-2B) to show that the well tap 32 has a higher conductivity level than the well region 35 . Jain, in a similar device to Maeda in view of Soussan, shows (see, e.g. , Jain: fig. 2B) that the well tap 218 (as P+ type, see, e.g. , Jain: col.5/I.47-54)]) has a higher conductivity level than the well region 203 (as P type, see, e.g. , Jain: col.4/I.27-34). Jain also shows (see, e.g. , Jain: fig. 2B) that the well tap 218 can be electrically isolated from the PFETs and NFETs on the same side of the deep isolation region, respectively, by shallow trench isolation (STI) regions 206 . Such well tap 218 can be contacted to facilitate biasing of the Pwells. Thus, for each FET, the Pwell and the section of insulator layer 205 below the channel region can effectively function as a gate conductor and gate dielectric and, thereby as a back gate (see, e.g. , Jain: col.5/I.50-59). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the well tap with higher conductivity level than the well region of Jain in the device of Maeda in view of Soussan in order to facilitate biasing of the wells. Regarding claim 13, Maeda in view of Soussan in view of Jain shows (see, e.g. , Maeda: figs. 2-4, and 6-10) that, within the stack, First fingers MD1 of first capacitor plates MP1 of at least some of the additional capacitors are offset vertically (for example, interdigitated capacitor plates MP1/MP4 for a capacitor MP1/MP4 where the capacitor plates are offset vertically) Second fingers MD4 of the second capacitor plates MP4 of at least some of the additional capacitors are offset vertically (for example, interdigitated capacitor plates MP1/MP4 for a capacitor MP1/MP4 where the capacitor plates are offset vertically) Regarding claim 14, Maeda in view of Soussan in view of Jain shows (see, e.g. , Maeda: figs. 2-4, and 6-10) that, at least some additional capacitors in the stack have different physical parameters (see, e.g. , Maeda: figs. 18-20). Regarding claim 15, Maeda in view of Soussan in view of Jain shows (see, e.g. , Maeda: figs. 2-4, and 6-10) that the different physical parameters include any of different finger lengths, different finger spacings, different finger widths, and different finger thicknesses. (see, e.g. , Maeda: figs. 18-20). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov . If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /TIBERIU DAN ONUTA/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 2 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 3 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 4 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 5 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 6 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 7 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 8 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 9 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 10 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 11 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 12 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 13 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 14 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 15 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 16 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 17 Art Unit: 2814 Application/Control Number: 18/668,706 (Non-Final Rejection) Page 18 Art Unit: 2814
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