Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to a restriction requirement mailed on 06/10/2026, the Applicant (i) elected Invention I (Group I) drawn to a method encompassing claims 1-17 without traverse, (ii) canceled claims 18-20 directed to non-elected Invention II (Group II) and (iii) added new claims 21-23 directed to the elected Group I on 06/17/2026 (“06-17-26 Response”).
The Applicant amended claims 8 and 9 in the 06-17-26 Response.
Elected claims 1-17 and 21-23 are examined below.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 05/20/2024 (“05-20-24 IDS”) and 09/16/2024 (“09-16-24 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 05-20-24 IDS and 09-16-24 IDS are being considered by the examiner.
Specification
The specification is objected to, because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD OF FORINMG GATE ISOLATION FOR MUTIGATE DEVICE
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-14, 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2020/0066600 A1 to Ok et al. (“Ok”).
Fig. of Ok has been annotated to support the rejections below:
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Regarding independent claim 11, Ok teaches a method comprising:
forming a first isolation structure 902, 402 (para [0050] - “Like the native oxide layer 902, oxide layer 402 can also be formed from SiO2.”; Figs. 11 and 12 show the native oxide 902 that interfaces the fin 202 and the native oxide 402 that interfaces the fin 204.) between a first semiconductor extension 202 from a substrate 102 and a second semiconductor extension 204 from the substrate 102 (para [0044] - “NFET fins 202…PET fins 202”; para [0032] - “…the wafer 102 is a bulk semiconductor wafer…”);
forming a second isolation structure 1002, 904 or 1002, 904, 602 (para [0053] - “an oxide 1002…Suitable oxides include, but are not limited to, flowable oxides such as hydrogen silsesquioxane (HSQ) solution in methyl isobutyl ketone (MIBK)…”; para [0052] - “Suitable dielectrics for layer 904 include…Al2O3, TiO2, ZrO2, HfO2 and/or MgO.”; para [0044] - “A conformal liner 602…Suitable liner material include…yttrium oxide (Y2O3), lutetium oxide (Lu2O3), lanthanum oxide (La2O3), strontium oxide (SrO)…”) over the first isolation structure 904, 402, wherein the second isolation structure 1002, 904 or 1002, 904, 602 includes a silicon-comprising dielectric bulk layer 1002 and a metal-and-oxygen comprising dielectric liner 904 or 904, 602, wherein the silicon-comprising bulk dielectric layer 1002 is wrapped by the metal-and-oxygen comprising dielectric liner 904 or 904, 602; and
wherein a first portion P1 of the second isolation structure 1002, 904 or 1002, 904, 602 is between a first gate 1702 and a second gate 1704 (para [0064] - “Replacement gates 1702 and 1704.”), a second portion P2 of the second isolation structure 1002, 904 or 1002, 904, 602 is between a first dielectric spacer 1304 (of 1702) (para [0059] - “Gate spacers 1304”) and a second dielectric spacer 1304 (of 1704), and a third portion P3 of the second isolation structure 1002, 904 or 1002, 904, 602 is between a first epitaxial source/drain 1402 (para [0061] - “…an epitaxial process is used to grow the source and drains 1402/1404 on the NFET/PFET fins 202/204, respectively.”) and a second epitaxial source/drain 1404.
Regarding claim 12, Ok teaches the forming of the first isolation structure 902, 402 and the forming of the second isolation structure 1002, 904 or 1002, 904, 602 that provide the first isolation structure 902, 402 and the second isolation structure 1002, 902 or 1002, 904, 602 with a first width w1 and a second width w2, respectively, wherein the first width w1 is greater than the second width w2.
Regarding claim 13, Ok teaches the forming of the second isolation structure 1002, 904 or 1002, 904, 602 that provides the metal-and-oxygen comprising dielectric layer 904 or 904, 602 of the first portion P1 of the second isolation structure 1002, 904 or 1002, 904, 602 with a first thickness along sidewalls of the silicon-comprising dielectric bulk layer 1002 and a second thickness along a bottom P3 of the silicon-comprising dielectric bulk layer 1002, wherein the first thickness is different than the second thickness.
Regarding claim 14, Ok teaches forming an isolation end cap 1502 (para [0062] - “a dielectric fill material 1502”) over the second isolation structure 1002, 904 or 1002, 904, 602, wherein the isolation cap 1502 is formed of a dielectric material.
Regarding independent claim 21, Ok teaches a method comprising:
forming a first isolation structure 902, 402 (para [0050] - “Like the native oxide layer 902, oxide layer 402 can also be formed from SiO2.”; Figs. 11 and 12 show the native oxide 902 that interfaces the fin 202 and the native oxide 402 that interfaces the fin 204.) between a first semiconductor extension 202 from a substrate 102 and a second semiconductor extension 204 from the substrate 102 (para [0044] - “NFET fins 202…PET fins 202”; para [0032] - “…the wafer 102 is a bulk semiconductor wafer…”);
forming a second isolation structure 1002, 904 or 1002, 904, 602 (para [0053] - “an oxide 1002…Suitable oxides include, but are not limited to, flowable oxides such as hydrogen silsesquioxane (HSQ) solution in methyl isobutyl ketone (MIBK)…”; para [0052] - “Suitable dielectrics for layer 904 include…Al2O3, TiO2, ZrO2, HfO2 and/or MgO.”; para [0044] - “A conformal liner 602…Suitable liner material include…yttrium oxide (Y2O3), lutetium oxide (Lu2O3), lanthanum oxide (La2O3), strontium oxide (SrO)…”) over the first isolation structure 904, 402, wherein the second isolation structure 1002, 904 or 1002, 904, 602 includes a silicon-comprising dielectric bulk layer 1002 and a metal-and-oxygen comprising dielectric liner 904 or 904, 602, wherein the silicon-comprising bulk dielectric layer 1002 is wrapped by the metal-and-oxygen comprising dielectric liner 904 or 904, 602; and
after forming the second isolation structure 1002, 904 or 1002, 904, 602, forming a first gate 1702 (para [0064] - “Replacement gates 1702 and 1704.”) over the first semiconductor extension 202, a second gate 1704 over the second semiconductor extension 204, a first epitaxial source/drain 1402 (para [0061] - “…an epitaxial process is used to grow the source and drains 1402/1404 on the NFET/PFET fins 202/204, respectively.”) over the first semiconductor extension 202, and a second epitaxial source/drain 1404 over the second semiconductor extension 204, wherein:
in a first cross-sectional view, a first portion P1 of the second isolation structure 1002, 904 or 1002, 904, 602 is between a first gate 1702 and a second gate 1704,
in a second cross-sectional view, a second portion P2 of the second isolation structure 1002, 904 or 1002, 904, 602 is between a first dielectric spacer 1304 (of 1702) (para [0059] - “Gate spacers 1304”) and a second dielectric spacer 1304 (of 1704), and
in a third cross-sectional view, a third portion P3 of the second isolation structure 1002, 904 or 1002, 904, 602 is between the first epitaxial source/drain 1402 (para [0061] - “…an epitaxial process is used to grow the source and drains 1402/1404 on the NFET/PFET fins 202/204, respectively.”) and the second epitaxial source/drain 1404.
Regarding claim 23, Ok teaches forming an isolation end cap 1502 (para [0062] - “a dielectric fill material 1502”) on the silicon-comprising dielectric bulk layer 1002 of the the second isolation structure 1002, 904 or 1002, 904, 602 after forming the first gate 1702 and the second gate 1704.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 1 is allowed, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, forming a second isolation structure in the upper portion of the trench by:
forming a metal-and-oxygen comprising dielectric liner over the sacrificial layer and the first isolation structure, wherein the metal-and-oxygen comprising dielectric linear partially fills the upper portion of the trench, and
forming a silicon-comprising dielectric layer over the metal-and-oxygen comprising dielectric liner, wherein the silicon-comprising dielectric layer fills a remainder of the upper portion of the trench; and
replacing the sacrificial layer, a portion of the first stack of layers, and a portion of the second stack of layers with one or more gate layers.
Claims 2-10 are allowed, because they depend from the allowed independent claim 1.
Claim 15 is objected to for depending on a rejected base claim 11, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 11 or the base claim 11 is amended to include all of the limitations of claim 15.
Claims 16 and 17 are allowable for depending on the allowable claim 11.
Claim 22 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 22.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2020/0357703 A1 to Lee et al.
Pub. No. US 2020/0279918 A1 to Wu et al.
Pub. No. US 2020/0105871 A1 to Glass et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 30 June 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
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