DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), fourth paragraph:
Subject to the [fifth paragraph of 35 U.S.C. 112 (pre-AIA )], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 9 recites the limitation “The device of claim o”, however the claims filed on 7/1/2024 do not disclose claim o. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Examiner interprets “The device of claim o” to mean “The device of claim 1”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun et al. (US 2018/0047634) (hereafter Jun).
Regarding claim 17, Jun discloses a device comprising:
a semiconductor substrate (element number is not shown in Fig. 5C but see 12 in Fig. 3A, paragraph 0033);
a shallow trench isolation region 53 (Fig. 5C, paragraph 0039) extending into the semiconductor substrate;
a first epitaxy region (SD1 in Fig. 5C, paragraph 0031) and a second epitaxy region (SD2 in Fig. 5C, paragraph 0031) over the semiconductor substrate; and
a dielectric region (INS in Fig. 5C, paragraph 0040) sandwiched between the first epitaxy region (SD1 in Fig. 5C) and the second epitaxy region (SD2 in Fig. 5C), wherein a portion (bottom portion of 54 in Fig. 5C) of the dielectric region is lower than a bottom surface (bottom surface of 53 near upper portion of SD1 in Fig. 5C) of the shallow trench isolation region 53 (Fig. 5C), and wherein the dielectric region (INS in Fig. 5C) comprises:
a first seam 88s (Fig. 5C, paragraph 0046); and
a second seam 54s (Fig. 5C, paragraph 0046), wherein the first seam 88s (Fig. 5C) is spaced apart from the second seam 54s (Fig. 5C).
Regarding claim 18, Jun further discloses the device of claim 17, wherein the first seam 88s (Fig. 5C) extends from a top surface of the dielectric region (INS in Fig. 5C) into the dielectric region.
Regarding claim 19, Jun further discloses the device of claim 17, wherein in a top view of the device, the first seam 88s (Fig. 5C) is elongated (see Fig. 5B, wherein 88s is elongated in stacking direction), and is in middle between opposing sidewalls of the dielectric region (INS in Fig. 5C).
Regarding claim 20, Jun further discloses the device of claim 17, wherein the dielectric region (INS in Fig. 5C) comprises a lower portion 54 (Fig. 5C) and an upper portion 88C (Fig. 5C) overlapping the lower portion 54 (Fig. 5C), wherein the lower portion 54 (Fig. 5C) forms an interface with the upper portion 88C (Fig. 5C), and wherein the first seam 88s (Fig. 5C) is spaced apart from the second seam 54s (Fig. 5C) by a bottom part of the upper portion 88C (Fig. 5C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (US 2018/0047634) (hereafter Jun), in view of Yao et al. (US 2020/0328121) (hereafter Yao).
Regarding claim 1, Jun discloses a device comprising:
a semiconductor substrate (3, 12, and 18a in Fig. 3C, paragraphs 0022-0023) comprising a semiconductor region 18a (Fig. 3C, paragraph 0023);
a shallow trench isolation region 10 (Fig. 3C, paragraph 0024), wherein the semiconductor region 18a (Fig. 3C) is aside of, and is higher than, the shallow trench isolation region 10 (Fig. 3C);
a gate stack (74 and 76 in Fig. 3C, paragraph 0028) comprising:
a first portion (portion of 74 and 76 vertically above 18a in Fig. 3C) on the semiconductor region 18a (Fig. 3C); and
a second portion (portion of 74 and 76 vertically above 10 in Fig. 3C) overlapping the shallow trench isolation region 10 (Fig. 3C);
a dielectric region (INS in Fig. 3A, paragraph 0040) comprising a portion overlapping (see Fig. 3A, wherein INS laterally overlapping 10) the shallow trench isolation region 10 (Fig. 3A), wherein the dielectric region (INS in Fig. 5C) comprises:
a lower portion (52 and 55 in Fig. 5C, paragraph 0040); and
an upper portion 88c (Fig. 5C, paragraph 0046).
Jun does not disclose a part of the lower portion of the dielectric region is lower than a bottom surface of the shallow trench isolation region.
Yao discloses a part of the lower portion of the dielectric region 60 (Fig. 9, paragraph 0065) is lower than a bottom surface of the shallow trench isolation region 28 (Fig. 9, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun to form a part of the lower portion of the dielectric region is lower than a bottom surface of the shallow trench isolation region, as taught by Yao, since the dielectric fill material 60 (Yao, Fig. 9, paragraph 0066) can be composed of, for example, a flowable oxide or other similar material that is capable of providing electrical isolation between active devices.
Regarding claim 2, Jun further discloses the device of claim 1, wherein the lower portion (52 and 55 in Fig. 5C) and the upper portion 88c (Fig. 5C) of the dielectric region (INS in Fig. 5C) have a distinguishable interface therebetween.
Regarding claim 3, Jun further discloses the device of claim 1, wherein the lower portion (52 and 55 in Fig. 5C) comprises a first seam 54s (Fig. 5C, paragraph 0046) therein, and the upper portion 88c (Fig. 5C) comprises a second seam 88s (Fig. 5C, paragraph 0046) therein, and wherein the first seam 54s (Fig. 5C) is spaced apart from the second seam 88s (Fig. 5C) by a bottom part of the upper portion 88c (Fig. 5C) of the dielectric region (INS in Fig. 5C).
Regarding claim 4, Jun further discloses the device of claim 3 further comprising: a source/drain region (SD1 in Fig. 5C, paragraph 0031) aside of the gate stack (74 and 76 in Fig. 5C); and a source/drain contact plug (CS in Fig. 5C, paragraph 0029) over and electrically coupling to the source/drain region (SD1 in Fig. 5C), wherein the second seam 88s (Fig. 5C) extends to a top surface level of the source/drain contact plug (CS in Fig. 5C).
Regarding claim 5, Jun further discloses the device of claim 3, wherein a portion of the second seam 88s (Fig. 5C) is higher than a top surface of the gate stack (74 and 76 in Fig. 5C).
Regarding claim 6, Jun in view of Yao discloses the device of claim 1, however Jun does not disclose the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region.
Yao discloses the dielectric region 60 (Fig. 9, paragraph 0065) comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region 28 (Fig. 9, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun to form the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region, as taught by Yao, since the dielectric fill material 60 (Yao, Fig. 9, paragraph 0066) can be composed of, for example, a flowable oxide or other similar material that is capable of providing electrical isolation between active devices.
Regarding claim 7, Jun further discloses the device of claim 1, wherein in a cross-section of the device, the upper portion 88c (Fig. 5C, paragraph 0046) comprises a U-shapes bottom surface.
Regarding claim 8, Jun further discloses the device of claim 1 further comprising a first protruding semiconductor fin 18a (Fig. 2C, paragraph 0030) and a second protruding semiconductor fin 18b (Fig. 2C, paragraph 0030) having lengthwise directions aligned to a same straight line, wherein the dielectric region (see INS in Fig. 3A) separates the first protruding semiconductor fin 18a (Fig. 3A) from the second protruding semiconductor fin 18b (Fig. 3A).
Regarding claim 9, Jun further discloses the device of claim o further comprising:
a first Fin Field-Effect Transistor (FinFET) (TR1 in Fig. 3A, paragraph 0033) comprising the first protruding semiconductor fin 18a (Fig. 3A) and a first source/drain region (SD1 in Fig. 3A, paragraph 0033), wherein the first source/drain region (SD1 in Fig. 3A) is between the first protruding semiconductor fin 18a (Fig. 3A) and the dielectric region (INS in Fig. 3A); and a second FinFET (TR2 in Fig. 3A, paragraph 0033) comprising the second protruding semiconductor fin 18b (Fig. 3A) and a second source/drain region (SD2 in Fig. 3A, paragraph 0033), wherein the second source/drain region (SD2 in Fig. 3A) is between the second protruding semiconductor fin 18b (Fig. 3A) and the dielectric region (INS in Fig. 3A).
Regarding claim 10, Jun further discloses the device of claim 1 further comprising a gate spacer 38 (Fig. 3A, paragraph 0040) contacting the dielectric region (INS in Fig. 3A) to form a vertical interface (interface between 38 and INS in Fig. 3A), wherein the vertical interface (interface between 38 and INS in Fig. 3A) extends to a level higher than a top surface of the gate stack (74 and 76 in Fig. 3A).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of Yao as applied to claim 1 above, and further in view of Yu et al. (US 2020/0152736) (hereafter Yu).
Regarding claim 11, Jun in view of Yao discloses the device of claim 1, however Jun and Yao does not disclose a dielectric layer overlapping and contacting the gate stack, wherein the dielectric layer comprises a vertical seam therein.
Yu discloses a dielectric layer (160 and 170 in Fig. 10B, paragraphs 0037-0038) overlapping and contacting the gate stack (140A and 140B in Fig. 10B, paragraph 0038), wherein the dielectric layer (160 and 170 in Fig. 10B) comprises a vertical seam 182 (Fig. 10B, paragraph 0038) therein.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun in view of Yao to form a dielectric layer overlapping and contacting the gate stack, wherein the dielectric layer comprises a vertical seam therein, as taught by Yu, since air gap 182 (Yu, Fig. 10B, paragraph 0038) distance between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), i.e., work function metal 142 (Yu, Fig. 10B, paragraph 0038), is relatively large, which advantageously enlarges space between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), reducing cross-talk.
Claims 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (US 2018/0047634) (hereafter Jun), in view of Yu et al. (US 2020/0152736) (hereafter Yu).
Regarding claim 12, Jun discloses a device comprising:
a semiconductor substrate (3, 12, and 18a in Fig. 3C, paragraphs 0022-0023) comprising a semiconductor region 18a (Fig. 3C, paragraph 0023);
a shallow trench isolation region 6 (Fig. 3C, paragraph 0024), wherein the semiconductor region 18a (Fig. 3C) is aside of, and is higher than, the shallow trench isolation region 6 (Fig. 3C);
a gate stack (GS in Fig. 3A, paragraph 0027) on the semiconductor region 18a (Fig. 3A);
a first epitaxy region (SD1 in Fig. 5C, paragraph 0031) and a second epitaxy region (SD2 in Fig. 5C, paragraph 0031) extending into the semiconductor region (element number is not shown in Fig. 5C but see 18a in Fig. 3A); and
a dielectric region (INS in Fig. 5C, paragraph 0040) laterally between the first epitaxy region (SD1 in Fig. 5C) and the second epitaxy region (SD2 in Fig. 5C), wherein the dielectric region (INS in Fig. 5C) comprises:
a first portion (52 and 55 in Fig. 5C, paragraph 0040); and
a second portion 88c (Fig. 5C, paragraph 0046) over and contacting the first portion (52 and 55 in Fig. 5C) to form an interface (interface between 88c and 55 in Fig. 5C), wherein the interface (interface between 88c and 55 in Fig. 5C) is higher than a bottom surface of the first epitaxy region (SD1 in Fig. 5C), and wherein at least one of the first portion and the second portion 88c (Fig. 5C) of the dielectric region (INS in Fig. 5C) comprises a second seam 88s (Fig. 5C, paragraph 0046).
Jun does not disclose a dielectric layer over and contacting the gate stack, wherein the dielectric layer comprises a first seam therein.
Yu discloses a dielectric layer (160 and 170 in Fig. 10B, paragraphs 0037-0038) over and contacting the gate stack (140A and 140B in Fig. 10B, paragraph 0038), wherein the dielectric layer (160 and 170 in Fig. 10B) comprises a first seam 182 (Fig. 10B, paragraph 0038) therein.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun to form a dielectric layer over and contacting the gate stack, wherein the dielectric layer comprises a first seam therein, as taught by Yu, since air gap 182 (Yu, Fig. 10B, paragraph 0038) distance between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), i.e., work function metal 142 (Yu, Fig. 10B, paragraph 0038), is relatively large, which advantageously enlarges space between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), reducing cross-talk.
Regarding claim 16, Jun further discloses the device of claim 12, wherein the first portion (52 and 55 in Fig. 5C) and the second portion 88c (Fig. 5C) of the dielectric region (INS in Fig. 5C) have a same width (see Fig. 5C, wherein horizontal length of 52 and 55 is same as the horizontal length of 88c).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of Yu as applied to claim 12 above, and further in view of Yao et al. (US 2020/0328121) (hereafter Yao).
Regarding claim 13, Jun in view of Yu discloses the device of claim 12, however Jun and Yu do not disclose the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region.
Yao discloses the dielectric region 60 (Fig. 9, paragraph 0065) comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region 28 (Fig. 9, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun in view of Yu to form the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region, as taught by Yao, since the dielectric fill material 60 (Yao, Fig. 9, paragraph 0066) can be composed of, for example, a flowable oxide or other similar material that is capable of providing electrical isolation between active devices.
Regarding claim 14, Jun (utilized different elements for a second seam as applied in claim 12 in the above) discloses a device comprising:
a semiconductor substrate (3, 12, and 18a in Fig. 3C, paragraphs 0022-0023) comprising a semiconductor region 18a (Fig. 3C, paragraph 0023);
a shallow trench isolation region 6 (Fig. 3C, paragraph 0024), wherein the semiconductor region 18a (Fig. 3C) is aside of, and is higher than, the shallow trench isolation region 6 (Fig. 3C);
a gate stack (GS in Fig. 3A, paragraph 0027) on the semiconductor region 18a (Fig. 3A);
a first epitaxy region (SD1 in Fig. 5C, paragraph 0031) and a second epitaxy region (SD2 in Fig. 5C, paragraph 0031) extending into the semiconductor region (element number is not shown in Fig. 5C but see 18a in Fig. 3A); and
a dielectric region (INS in Fig. 5C, paragraph 0040) laterally between the first epitaxy region (SD1 in Fig. 5C) and the second epitaxy region (SD2 in Fig. 5C), wherein the dielectric region (INS in Fig. 5C) comprises:
a first portion (52 and 55 in Fig. 5C, paragraph 0040); and
a second portion 88c (Fig. 5C, paragraph 0046) over and contacting the first portion (52 and 55 in Fig. 5C) to form an interface (interface between 88c and 55 in Fig. 5C), wherein the interface (interface between 88c and 55 in Fig. 5C) is higher than a bottom surface of the first epitaxy region (SD1 in Fig. 5C), and wherein at least one of the first portion (52 and 55 in Fig. 5C) and the second portion of the dielectric region (INS in Fig. 5C) comprises a second seam 54s (Fig. 5C, paragraph 0046); and
wherein the first portion (52 and 55 in Fig. 5C) comprises the second seam 54s (Fig. 5C) therein.
Jun does not disclose a dielectric layer over and contacting the gate stack, wherein the dielectric layer comprises a first seam therein.
Yu discloses a dielectric layer (160 and 170 in Fig. 10B, paragraphs 0037-0038) over and contacting the gate stack (140A and 140B in Fig. 10B, paragraph 0038), wherein the dielectric layer (160 and 170 in Fig. 10B) comprises a first seam 182 (Fig. 10B, paragraph 0038) therein.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun to form a dielectric layer over and contacting the gate stack, wherein the dielectric layer comprises a first seam therein, as taught by Yu, since air gap 182 (Yu, Fig. 10B, paragraph 0038) distance between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), i.e., work function metal 142 (Yu, Fig. 10B, paragraph 0038), is relatively large, which advantageously enlarges space between metal gates 140A, 140B (Yu, Fig. 10B, paragraph 0038), reducing cross-talk.
Jun and Yu do not disclose the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region.
Yao discloses the dielectric region 60 (Fig. 9, paragraph 0065) comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region 28 (Fig. 9, paragraph 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Jun in view of Yu to form the dielectric region comprises a bottom portion lower than a bottommost surface of the shallow trench isolation region, as taught by Yao, since the dielectric fill material 60 (Yao, Fig. 9, paragraph 0066) can be composed of, for example, a flowable oxide or other similar material that is capable of providing electrical isolation between active devices.
Regarding claim 15, Jun further discloses the device of claim 13, wherein the second portion 88c (Fig. 5C) comprises the second seam therein 88s (Fig. 5C).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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