DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (U.S. PGPub 2019/0259844) in view of Akram (U.S. PGPub 2005/0181595).
Regarding claim 1, Sharma teaches a method for manufacturing a semiconductor device, comprising:
forming source/drain contacts (Fig. 1D, [0036], 104), forming barrier regions, the barrier regions including a material that absorbs hydrogen (108, [0028]), and forming a channel layer on the barrier regions (Fig. 2A, [0048], 102),
forming a gate dielectric layer including a first gate dielectric layer and a second gate dielectric layer made of different materials ([0046]), and
forming a work function metal layer on the gate dielectric layer ([0047]),
such that the barrier regions separate the source/drain contacts from the channel layer ([0041], embodiments of Fig. 2 may comprise any source/drain contact embodiment of Fig. 1; the embodiment of Fig. 1D has the barrier region separating the source/drain contacts from the channel layer, see annotated figures below);
the channel material including an oxide semiconductor material ([0025]);
wherein formation of the barrier regions includes forming barrier sections respectively on upper surfaces of the source/drain contacts, forming pairs of barrier sidewalls, such that after forming the source/drain contacts the pairs of barrier sidewalls are formed to surround the source/drain contacts, respectively (see annotated figures below).
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Sharma does not explicitly teach wherein forming the barrier sections and forming the pairs of the barrier sidewalls are performed in two different steps.
Sharma is silent on the specific method of forming the barrier but teaches wherein the barrier is formed using any known suitable techniques ([0059]).
Akram teaches forming a contact comprising barrier regions, wherein formation of the barrier regions includes forming a barrier section respectively on upper surfaces of the contact, forming pairs of barrier sidewalls, such that after forming the contacts the pairs of barrier sidewalls are formed to surround the contact, wherein forming the barrier section and forming the pairs of the barrier sidewalls are performed in two different steps (Fig. 8, reproduced below; barrier sidewalls 60, barrier section 66, [0053]; different steps [0054]).
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Akram with Sharma such that forming the barrier sections and forming the pairs of the barrier sidewalls are performed in two different steps for the purpose of forming the structure of Sharma according to a known suitable method (Akram, [0054]).
Regarding claim 4, the combination of Sharma and Akram teaches forming a gate dielectric on the channel layer and forming a gate electrode on the work function metal layer opposite to the gate dielectric layer (Sharma, Fig. 2A, gate dielectric 116, gate electrode 118, [0041]; [0047], gate electrode fill layer in stack with work function metal layer). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma and Akram for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Sharma and Akram does not explicitly teach wherein a minimum distance between two adjacent ones of the barrier regions is larger than 15 nanometers. Examiner takes official notice that channel length for TFTs is commonly greater than 50 or 100 nanometers. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Sharma and Akram such that a minimum distance between two adjacent ones of the barrier regions is larger than 15 nanometers for the purpose of choosing an appropriate channel length for the transistor.
Claims 6-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (U.S. PGPub 2019/0259844) in view of Akram (U.S. PGPub 2005/0181595) and Zhang (U.S. PGPug 2015/0357477).
Regarding claim 6, Sharma teaches a method for manufacturing a semiconductor device, comprising:
forming source/drain contacts, each surrounded by a pair of barrier sidewalls and covered by a barrier section which make up respective barrier regions (Fig. 1D, [0036], contacts 104, barrier 108), the barrier regions including a material that receives hydrogen ([0028]), and
forming a channel layer on the barrier section, ([0041], Fig. 2A, embodiments of Fig. 2 may comprise any source/drain contact embodiment of Fig. 1; see annotated figure below); the channel layer including an oxide semiconductor material ([0025]).
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Sharma does not explicitly teach wherein the method comprises forming trenches in a dielectric layer, forming the pair of barrier sidewalls in at least one of the trenches such that at least portions of bottom surfaces of the trenches are formed by the dielectric layer; forming the source/drain contacts respectively in the trenches so as to permit at least one of the source/drain contacts to be surrounded by the pair of barrier sidewalls; after forming the source/drain contacts, forming the barrier section which covers the source/drain contacts; wherein the barrier section has an upper surface that is flush with an upper surface of the dielectric layer.
Sharma is silent on the specific method of forming the barrier but teaches wherein the barrier is formed using any known suitable techniques ([0059]) and further teaches wherein the source/drain contacts are formed over an interlayer dielectric ([0044]).
Zhang teaches forming source/drain contacts for a transistor having a similar structure to Fig. 2A of Sharma (Figs. 1-2, [0026]), comprising forming trenches in a dielectric layer such that the bottom of the trench is formed by the dielectric layer, and forming the source/drain contacts in the trench (Figs. 2D-2F, [0030]-[0032]).
Akram teaches a method of forming a contact, comprising forming a trench in a dielectric layer, forming a pair of barrier sidewalls in the trench (Fig. 4, dielectric 54, trench 56, barrier sidewalls 60, [0046]-[0048]);
forming the contact in the trench so as to permit the contact to be surrounded by the pair of barrier sidewalls (Fig. 5, 62, [0050]);
after forming the source/drain contacts, forming the barrier section which covers the source/drain contacts, wherein the barrier section has an upper surface that is flush with an upper surface of the dielectric layer (Fig. 8, reproduced below, 66, [0053]-[0054]).
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Akram with Sharma such that the method comprises forming trenches in a dielectric layer, forming the pair of barrier sidewalls in at least one of the trenches such that the dielectric layer is exposed from bottom surfaces of the trenches; forming the source/drain contacts respectively in the trenches so as to permit at least one of the source/drain contacts to be surrounded by the pair of barrier sidewalls; after forming the source/drain contacts, forming the barrier section which covers the source/drain contacts; wherein the barrier section has an upper surface that is flush with an upper surface of the dielectric layer for the purpose of forming the structure of Sharma according to a known suitable method (Akram, [0054]) wherein the source/drain contacts are isolated from the semiconductor substrate (Sharma, [0044], Zhang, [0030]).
Regarding claim 7, the combination of Sharma, Akram, and Zhang teaches wherein the oxide semiconductor material includes indium gallium zinc oxide, indium zinc oxide, indium tin oxide, gallium oxide, or indium oxide (Sharma, [0025]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 8, the combination of Sharma, Akram, and Zhang teaches forming a gate dielectric on the channel layer and forming a gate electrode on the gate dielectric layer (Sharma, Fig. 2A, gate dielectric 116, gate electrode 118, [0041]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 9, the combination of Sharma, Akram, and Zhang teaches wherein the gate dielectric layer is formed after forming the channel layer (Sharma, Fig. 2A, [0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 10, the combination of Sharma, Akram, and Zhang teaches wherein the gate electrode layer is formed after forming the channel layer (Sharma, Fig. 2A, [0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 11, the combination of Sharma, Akram, and Zhang teaches wherein the source/drain contacts are formed in the dielectric layer using a Damascene process (Akram, [0050]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 12, the combination of Sharma, Akram, and Zhang teaches wherein the source/drain contacts are formed after forming the pair of barrier sidewalls (Akram, Figs. 5-6). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 13, the combination of Sharma, Akram, and Zhang teaches wherein the at least one of the source/drain contacts has a lower surface which is opposite to the barrier section (see annotated figures in rejection of claim 6), wherein the source/drain contact is in direct contact with a dielectric layer (Sharma, [0044], substrate 114 may be ILD; see Spec at [0035], ILD layer 400 may comprise multiple films), wherein the source/drain contacts are formed after forming the pair of barrier sidewalls (Akram, Figs. 5-6). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 14, the combination of Sharma, Akram, and Zhang teaches wherein each of the source/drain contacts includes tungsten, ruthenium, copper, tantalum nitride, titanium nitride, or combinations thereof (Sharma, [0026]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Regarding claim 15, Sharma teaches a method for manufacturing a semiconductor device, comprising: forming source/drain contacts, each surrounded by a pair of barrier sidewalls made of a first material that receives hydrogen and covered by a barrier section made of a second material that receives hydrogen (Fig. 1D, [0036], contacts 104, barrier 108, [0028]), and after forming barrier sections, forming a channel layer on the barrier sections ([0041], Fig. 2A, embodiments of Fig. 2 may comprise any source/drain contact embodiment of Fig. 1; see annotated figure below); the channel layer including an oxide semiconductor material ([0025]).
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Sharma does not explicitly teach wherein the method comprises forming trenches in a dielectric layer, the trenches not extending completely through the dielectric layer, forming a barrier layer over the dielectric layer, and having an upper barrier portion formed on an upper surface of the dielectric layer, bottom barrier portions which are respectively formed on bottom surfaces of the trenches, and pairs of sidewall barrier portions, which are respectively formed on lateral surfaces of the trenches; removing the upper barrier portion and the bottom barrier portions; and after removing the upper barrier portion and the bottom barrier portions, forming source/drain contacts respectively in the trenches so that the source/drain contacts are respectively surrounded by the pairs of sidewall barrier portions.
Sharma is silent on the specific method of forming the barrier but teaches wherein the barrier is formed using any known suitable techniques ([0059]) and further teaches wherein the source/drain contacts are formed over an interlayer dielectric ([0044]).
Zhang teaches forming source/drain contacts for a transistor having a similar structure to Fig. 2A of Sharma (Figs. 1-2, [0026]), comprising forming trenches in a dielectric layer such that the bottom of the trench is formed by the dielectric layer, and forming the source/drain contacts in the trench (Figs. 2D-2F, [0030]-[0032]).
Akram teaches a method of forming a contact, comprising:
forming trenches in a dielectric layer, forming a barrier layer over the dielectric layer, and having an upper barrier portion formed on an upper surface of the dielectric layer, bottom barrier portions which are respectively formed on bottom surfaces of the trenches, and pairs of sidewall barrier portions, which are respectively formed on lateral surfaces of the trenches (Fig. 4, dielectric 54, trench 56, barrier layer 61, [0046]-[0049]),
removing the upper barrier portion and the bottom barrier portions (Fig. 5, barrier sidewalls 60, [0046]-[0049]), and
after removing the upper barrier portion and the bottom barrier portions, forming a contact respectively in the trenches so that contact is respectively surrounded by the pairs of sidewall barrier portions (Fig. 8, reproduced below, 64, [0053]-[0054]).
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Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Akram with Sharma such that the method comprises forming trenches in a dielectric layer, the trenches not extending completely through the dielectric layer, forming a barrier layer over the dielectric layer, and having an upper barrier portion formed on an upper surface of the dielectric layer, bottom barrier portions which are respectively formed on bottom surfaces of the trenches, and pairs of sidewall barrier portions, which are respectively formed on lateral surfaces of the trenches; removing the upper barrier portion and the bottom barrier portions; and after removing the upper barrier portion and the bottom barrier portions, forming source/drain contacts respectively in the trenches so that the source/drain contacts are respectively surrounded by the pairs of sidewall barrier portions for the purpose of forming the structure of Sharma according to a known suitable method (Akram, [0054]) wherein the source/drain contacts are isolated from the semiconductor substrate (Sharma, [0044], Zhang, [0030]).
Regarding claim 16, the combination of Sharma, Akram, and Zhang teaches wherein each of the first material and the second material includes indium gallium zinc oxide, indium zinc oxide, zinc oxide, indium tin oxide, indium oxide, gallium oxide, indium gallium silicon zinc oxide, or combinations thereof (Sharma, [0027]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 15.
Regarding claim 17, the combination of Sharma, Akram, and Zhang teaches wherein the oxide semiconductor material includes indium gallium zinc oxide, indium zinc oxide, indium tin oxide, gallium oxide, or indium oxide (Sharma, [0025]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 15.
Regarding claims 18 and 20, the combination of Sharma, Akram, and Zhang teaches wherein each of the source/drain contacts includes tungsten, ruthenium, copper, tantalum nitride, titanium nitride, or combinations thereof (Sharma, [0026]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 15.
Regarding claim 19, the combination of Sharma, Akram, and Zhang teaches wherein after forming barrier sections, barrier regions are formed, each of the barrier regions being dimensioned to be Π-shaped, and including one of the barrier sections and a respective one of the pairs of the sidewall barrier portions (Sharma, Fig. 1D, Fig. 2A, see previous annotated figure). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 15.
Regarding claim 21, the combination of Sharma, Akram, and Zhang teaches wherein forming the pair of barrier sidewalls includes conformally forming a barrier material layer on the dielectric layer along inner surfaces of the trenches (Akram, Fig. 4, [0046]-[0049] and performing an anisotropic etching process to remove portions of the barrier material layer on a top surface of the dielectric layer and on bottom surfaces of the trenches so as to form the pair of barrier sidewalls in the at least one of the trenches (Akram, Fig. 5, [0046]-[0049]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Sharma, Akram, and Zhang for the reasons set forth in the rejection of claim 6.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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