DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 10-12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the reset circuit being operative to reset the first plurality of cells in the first sub-block in parallel comprises the reset circuit being operative to: generate a reset signal as a logical disjunction of a first signal indicating an initiation of a power up duration of the first plurality of cells and a second signal indicating a completion of the power up duration of the first plurality of cells; and trigger, through the reset signal, a reset of a bit value stored in each of the first plurality of cells to a predetermined bit value in parallel during the power up duration; while in regard to claim 11, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the reset circuit being operative to reset each of the first plurality of cells comprises the reset circuit being operative to reset a bit value stored in each of the first plurality of cells to a bit value zero during a power up duration; while in regard to claim 12 , the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the reset circuit further comprises a power control circuit operative to: generate a first signal indicating an initiation of a power up duration of the plurality of cells; and generate a second signal indicating a completion of the power up duration of the plurality of cells.
Claim(s) 13-14 depend from claim 12, and as such are also objected for the same reasons.
Allowable Subject Matter
Claim(s) 2-9 and 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, such as US 9576663, US 10636464, US 20070240089, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 2 and 3.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 9576663 to Gazit et al. (“Gazit”) in view of U.S. Patent/Publication No. 10636464 to Wu et al. (“Wu”).
As to claim 1, Gazit teaches substantially the claimed invention, including: A memory device (As found in at least FIG. 1 and the Abstract) comprising a cell array comprising a plurality of cells, each of the plurality of cells operative to store a bit value (While the teachings of Gazit expressly include memory types such as SRAM and DRAM or CAM, as found in at least Column 1, lines 39-45, it is well-known and well-understood that these memory type include a plurality of memory cells, each operable to store at least a bit value); and a reset circuit connected to the cell array, wherein the reset circuit is operative to: partition the plurality of cells in a first sub-block and a second sub-block (As found in at least FIGS. 1-2 and at least Column 4, lines 60-67 and Column 5, lines 1-21, “reset” circuit 120 is coupled to array 110 and operative to partition array 110 into sub-blocks (Sub Array [0:n-1]); FIG. 2 shows a simple example in which single-port memory device 110 is partitioned into four sub-arrays 111 (labelled 0, . . . , 3)).
While Gazit may not expressly teach reset a first plurality of cells in the first sub-block in parallel, and reset a second plurality of cells in the second sub-block in parallel, the teachings of Gazit are operative to target sub-arrays of a memory device 110, individually or in groups, as found in at least FIG. 2.
Moreover, relevantly and complementarily, Wu teaches reset a first plurality of cells in the first sub-block in parallel, and reset a second plurality of cells in the second sub-block in parallel (In relevant art of memory devices, as found in at least claim 1, in brief and saliently: A memory device, comprising: a first memory array, comprising a plurality of first memory units; a second memory array, comprising a plurality of second memory units; a read/write circuit … configured to read, set or reset the first memory units and the second memory units; it is implicit that the reset is performed in parallel since the there are a plurality of first and second memory units).
Gazit and Wu are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory devices that may have arrays that are further sub-divided into sub-arrays, and operated upon.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Gazit as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Wu also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: the teachings of Gazit include sub-arrays of a memory device that can be data-accessed and operated upon, individually, or in groups; Wu, further teaches that a memory device may comprise at least first and second arrays that can be accessed and operated upon, including reset operations. The memory device in the teachings of Gazit, before the effective filing date of the present Application, would have easily incorporated the further operation of sub-array reset.
Therefore, it would have been obvious to combine Gazit with Wu to make the above modification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1, 2 and 3 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim(s) 13 of U.S. Patent No. 11238923; unpatentable over at least claim(s) 4 of U.S. Patent No. 11990180. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are obviated by the patented claims. A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over (in a non-statutory double patent rejection) the earlier claim. In re Lonqi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Bercl, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). Ely Lilly and Co. v Bar Laboratories, Inc., United States Court of Appeals for the Federal Circuit, on petition for rehearing en banc (decided: May 30, 2001).The instant claims are obviated by the patented claims; the patent and the application claim obvious common subject matter: a memory device, comprising, in brief and saliently: A memory device comprising a cell array comprising a plurality of cells, each of the plurality of cells operative to store a bit value; a reset circuit connected to the cell array, wherein the reset circuit is operative to: partition the plurality of cells in a first sub-block and a second sub-block, reset a first plurality of cells in the first sub-block in parallel, and reset a second plurality of cells in the second sub-block in parallel. And, as required further in claims 2 and 3, respectively: a power control circuit operative to generate a first signal indicating an initiation of a power up duration of the plurality of cells and a second signal indicating a completion of the power up duration of the plurality of cells; determining that a number of a plurality of cells in an array of a memory device is more than a predetermined number.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827