DETAILED ACTION
This Office action responds to Applicant’s invention filed on 05/21/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-5.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Osawa (US 2022/0005743).
Regarding claim 1, Osawa shows (see, e.g., Osawa: fig.5M and annotated fig. 5M) all aspects of a display device, comprising:
A semiconductor element 20 having a main electrode and a control electrode on a first main surface (the main electrode and the control electrode are not shown in fig. 5M, but they exist inside the semiconductor element 20, indicated in the annotated fig. 5M; the evidence is the seed layer that should be made on another electrode part inside the semiconductor element 20)
A terminal substrate 252/251/21 having a bonding terminal 27 to which a wire is to be bonded on a front surface and a relay terminal (see, e.g., Osawa: annotated fig. 5M) on a back surface
The bonding terminal 27 and the relay terminal being electrically connected to each other
wherein:
The bonding terminal 27 has an area larger than an area of the control electrode
The terminal substrate 252/21 (with a part of the element 251) is bonded to the semiconductor element 20 so that the control electrode and the relay terminal are in contact with each other
The terminal substrate 252/251/21 has a step on the back surface
A side surface of the semiconductor element 20 is in contact with the step
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Regarding claim 2, Osawa shows (see, e.g., Osawa: fig.5M and annotated fig. 5M) that:
The terminal substrate 252/251/21 has a thin plate portion including the relay terminal and a thick plate portion including the bonding terminal
A thickness of the thin plate portion is smaller than a thickness of the thick plate portion
A boundary between the thin plate portion and the thick plate portion corresponds to the step
The thin plate portion is bonded to the semiconductor element 20
Regarding claim 3, Osawa shows (see, e.g., Osawa: fig.5M and annotated fig. 5M) that the back surface of the terminal substrate 252/251/21 in the thick plate portion is flush with a second main surface of the semiconductor element 20.
Regarding claim 4, Osawa shows (see, e.g., Osawa: fig.5M and annotated fig. 5M) that the terminal substrate 252/251/21 has a protrusion forming the step on the back surface.
Regarding claim 5, Osawa shows (see, e.g., Osawa: fig.5M and annotated fig. 5M) that:
A resin package 6 covers the semiconductor element 20 and the terminal substrate 252/251/21
The resin package 6 and the terminal substrate 252/251/21 are made of a same material (see, e.g., Osawa: par. [0071] and [0080])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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