Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant’s election without traverse of Species I: FIGS. 1 -3(b), claims 1-18 in the reply filed on 08/07/2026 is acknowledged. Moreover, claims 4-15 are withdrawn from consideration because they are not read on FIGS. 1-3(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Chinese Patent No.: (CN110634870) (hereinafter `870) [refer to the machine’s translation version].
Re claim 1, `870, FIGS. 1-3(b) teaches a static random access memory SRAM cell, comprising: a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor on a substrate,
wherein the first pull-up transistor and the second pull-up transistor (PU-1/PU2, FIG. 2) are provided at a first height relative to the substrate,
wherein the first pull-down transistor, the second pull-down transistor (PW-1/PD-2), the first pass-gate transistor, and the second pass-gate transistor (PG-1/PG2, FIGS. 3(a)/3(b)) are provided at a second height different from the first height relative to the substrate,
wherein each of the first pull-up transistor, the second pull-up transistor, the first pull- down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor comprises a channel nanosheet (portion between S1/2 and D1/2, 1015, FIG. 11(a)) extending in a first direction substantially parallel to a surface of the substrate, as well as source/drain portions (SD-1/SD2) provided above and below the channel nanosheet respectively, and
wherein the first pull-down transistor (PD-1) is aligned with the first pull-up transistor (PU-1) in a vertical direction, and the second pull-down transistor (PD-2) is aligned with the second pull-up transistor (PU-1) in the vertical direction.
Re claim 2, `870, FIGS. 1-3(b) teaches the SRAM cell according to claim 1, wherein a width of at least one of the channel nanosheets of the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor in the first direction is different from widths of other channel nanosheets in the first direction (portion between S1/2 and D1/2).
Re claim 3, `870, FIGS. 1-3(b) teaches the SRAM cell according to The SRAM cell according to claim 2,
wherein the channel nanosheet of each of the first pull-down transistor and the second pull-down transistor (portion between S1/2 and D1/2 of [PD1/PD2]) has a first width in the first direction, and
wherein the channel nanosheet of each of the first pass-gate transistor and the second pass-gate transistor (portion between S1/2 and D1/2 of [PG1/PG2]) has a second width different from the first width in the first direction.
Re claim 16, `870, FIGS. 1-3(b) teaches a memory, comprising a plurality of SRAM cells according to claim 1.
Re claim 17, `870, FIGS. 1-3(b) teaches an electronic device, comprising the memory according to claim 16 and a processor operationally coupled with the memory (processor that manages the bit and word lines, page 40).
Re claim 18, `870, FIGS. 1-3(b) teaches the electronic device according to claim 17, wherein the electronic device comprises: a smart phone, a computer, a tablet computer, a wearable intelligence device, an artificial intelligence device, or a mobile power supply (page 40).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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