Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on TW113100897 filed on 01/09/2024.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 6, 8-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Busch et al. (US 20130093050 A1 – hereinafter Busch).
Regarding Claim 1, Busch teaches a semiconductor structure (see the entire document; annotated Fig. 14; specifically, ([0040] - [0053]), and as cited below), comprising:
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Busch – annotated Fig. 14
a substrate (12 – annotated Fig. 14 – [0040]) comprising an active area (14_1 – [0053]), a peripheral area (16_2 – [0053]), and a dummy area (16_1 – [0053]) between the active area (14_1) and the peripheral area (16_2);
a conductive structure ({18, 20} – [0038]) disposed in the substrate (12);
a dielectric layer (28 – [0047]) disposed on the substrate (12);
a supporting layer (30 – [0053]) disposed on the dielectric layer (28), wherein a thickness of the supporting layer (30) in the peripheral area (16_2) is smaller than the thickness of the supporting layer in the dummy area (16_1) (annotated Fig. 14 shows thickness of 30 in area 16_2 is smaller than the thickness of 30 in area 16_1);
a first conductive layer (56 – [0048]) disposed in the dummy area (16_1) and being in contact with the supporting layer (30); and
a second conductive layer (54 – [0048]) disposed in the active area (14_1), extending through the dielectric layer (28), and being in contact with the conductive structure ({18, 20}).
Regarding Claim 6, Busch teaches the semiconductor structure according to claim 1, wherein the supporting layer and the dielectric layer comprise materials with different etching rates ([0045]).
Regarding Claim 8, Busch teaches the semiconductor structure according to claim 1, wherein the supporting layer has a stepped portion at a boundary of the dummy area and the peripheral area (see annotated Fig. 14).
Regarding Claim 9, Busch teaches the semiconductor structure according to claim 8, wherein the stepped portion of the supporting layer has a recess, and the first conductive layer is disposed in the recess (see annotated Fig. 14).
Regarding Claim 10, Busch teaches the semiconductor structure according to claim 9, wherein a bottom surface of the recess and the conductive structure is separated by a distance (see annotated Fig. 14).
Regarding Claim 11, Busch teaches the semiconductor structure according to claim 9, wherein a bottom surface of the recess is higher than a top surface of the dielectric layer (see annotated Fig. 14).
Regarding Claim 12, Busch teaches the semiconductor structure according to claim 9, wherein a bottom surface of the recess is between a top surface and a bottom surface of the supporting layer (see annotated Fig. 14).
Regarding Claim 13, Busch teaches the semiconductor structure according to claim 1, wherein the supporting layer covers a portion of a sidewall of the first conductive layer (see annotated Fig. 14).
Regarding Claim 14, Busch teaches a semiconductor structure (see the entire document; annotated Fig. 14; specifically, ([0040] - [0053]), and as cited below), comprising:
providing a substrate (12 – annotated Fig. 14 – [0040]), wherein the substrate comprises an active area (14_1 – [0053]), a peripheral area (16_2 – [0053]), and a dummy (16_1 – [0053] area between the active area (14_1) and the peripheral area (16_2);
forming a conductive structure ({18, 20} – [0038]) in the substrate (12);
forming a dielectric layer (28 – [0047]) on the substrate (12);
forming a supporting layer (30 – [0053]) on the dielectric layer (28);
patterning the supporting layer, such that a thickness of the supporting layer (30) in the peripheral area (16_2) is smaller than a thickness of the supporting layer in the dummy area (16_1) (annotated Fig. 14 shows thickness of 30 in area 16_2 is smaller than the thickness of 30 in area 16_1);
forming a first conductive layer (56 – [0048]), such that the first conductive layer is in contact with the supporting layer (30); and
forming a second conductive layer (54 – [0048]), such that the second conductive layer (54) is in contact with the conductive structure ({18, 20}).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Busch.
Regarding claims 15-20, Busch teaches claim 14 from which claims 15-20 depend. The examiner takes an official notice (per MPEP 2144.03) that all method steps claimed in claims 15-20 are common and well known in the art, in order to inter alia easily modify operation parameters.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the teachings of what is well known into the Busch’s method.
The ordinary artisan would have been motivated to modify Busch in the manner set forth above for at least the purpose of utilizing known method steps to ensure successful completion of the method steps.
Allowable Subject Matter
Claims 2-5, 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The semiconductor structure according to claim 1, wherein the thickness of the supporting layer in the peripheral area accounts for 10% to 50% of the thickness of the supporting layer in the dummy area.
Regarding claim 3: The semiconductor structure according to claim 1, wherein a bottom surface of the first conductive layer is lower than or aligned with a top surface of the supporting layer.
Regarding claim 4: The semiconductor structure according to claim 3, wherein the bottom surface of the first conductive layer is higher than a bottom surface of the supporting layer.
Regarding claim 5: The semiconductor structure according to claim 1, further comprising: a dielectric stack disposed on the dielectric layer and the supporting layer and being in contact with the dielectric layer and the supporting layer.
Regarding claim 7: The semiconductor structure according to claim 1, wherein the supporting layer comprises silicon nitride, and the dielectric layer comprises silicon oxide.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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