Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 20-25 are rejected under 35 U.S.C. 102(a1) as being anticipated by Lu et al. (US 10,867,957; hereinafter Lu).
Regarding claim 20, Lu, in fig. 2B, discloses a semiconductor device, comprising: an interposer 106 (col. 3, lines 8-9); a substrate 100; and a shape-metal alloy (SMA) structure 210 disposed between the interposer 106 and substrate 100.
Regarding claim 21, Lu discloses further including a semiconductor package 106 (col. 3, lines 4-8) disposed over the interposer 106 opposite the substrate 100 (fig. 2B).
Regarding claim 22, Lu discloses further including a solder bump 104’ disposed between the interposer 106 and semiconductor package 106 (fig. 2B).
Regarding claim 23, Lu discloses further including an electrical component 106 (col. 3, lines 4-8) disposed between the interposer 106 and substrate 100 (fig. 2B).
Regarding claim 24, Lu discloses further including a solder bump 104’ disposed between the interposer 106 and substrate 100 (fig. 2B).
Regarding claim 25, Lu discloses further including a plurality of SMA structures 210 disposed between the interposer 106 and substrate 100, wherein one of the plurality of SMA structures 210 is disposed at each corner of the interposer 106 (figs. 7C-7D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 10,867,957) in view of Chen et al. (US 2018/0374821; hereinafter Chen).
Regarding claim 1, Lu, in figs. 2A-2B, discloses a method of making a semiconductor device, comprising: providing a semiconductor die 100; disposing a shape-metal alloy (SMA) structure 206 over the semiconductor die 100, wherein the SMA structure 206 is formed of Nickel-Titanium (col. 4, lines 17-21); disposing a solder bump 114 over the semiconductor die 100; disposing an electrical component (col. 2, lines 49-52) over the semiconductor die 100; disposing the semiconductor die 100 over a substrate 106 with the SMA structure 206, solder bump 114, and electrical component between the semiconductor die 100 and substrate 106; and reflowing the solder bump 114 (col. 4, lines 41-44).
Lu discloses a method of making a semiconductor device as above but fails to disclose the semiconductor die is an interposer die.
However, Chen discloses the semiconductor die 101 is an interposer die (fig.1 & [0023]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the interposer die as taught by Chen in order to provide support and connectivity for electronic components and devices mounted thereon.
Regarding claim 2, Lu discloses wherein reflowing the solder bump 114 expands the SMA structure 206 (fig. 2B).
Regarding claim 3, Lu discloses wherein the SMA structure shrinks while cooling after reflow (fig. 2B).
Regarding claim 4, Chen discloses further including disposing a semiconductor package 102 over the interposer 101 opposite the substrate 106 (fig. 1).
Regarding claim 5, Chen discloses further including reflowing the solder bump 107 for a second time after disposing the semiconductor package 102 over the interposer 101 (figs. 8F-8G).
Regarding claim 6, Lu discloses wherein a gap exists between the solder bump 114 and substrate 106 prior to reflow (figs. 2A-2B).
Regarding claim 7, Lu, in figs. 2A-2B, discloses a method of making a semiconductor device, comprising: providing a semiconductor die 100; disposing a shape-metal alloy (SMA) structure 206 over the semiconductor die 100, disposing a solder bump 114 over the semiconductor die 100; disposing the semiconductor die 100 over a substrate 106 with the SMA structure 206 and solder bump 114 between the semiconductor die 100 and substrate 106; and reflowing the solder bump 114 (col. 4, lines 41-44).
Lu discloses a method of making a semiconductor device as above but fails to disclose the semiconductor die is an interposer die.
However, Chen discloses the semiconductor die 101 is an interposer die (fig.1 & [0023]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the interposer die as taught by Chen in order to provide support and connectivity for electronic components and devices mounted thereon.
Regarding claim 8, Lu discloses wherein reflowing the solder bump 114 expands the SMA structure 206 (fig. 2B).
Regarding claim 9, Lu discloses wherein the SMA structure shrinks while cooling after reflow (fig. 2B).
Regarding claim 10, Chen discloses further including disposing a semiconductor package 102 over the interposer 101 opposite the substrate 106 (fig. 1).
Regarding claim 11, Chen discloses further including reflowing the solder bump 107 for a second time after disposing the semiconductor package 102 over the interposer 101 (figs. 8F-8G).
Regarding claim 12, Lu discloses wherein a gap exists between the solder bump 114 and substrate 106 prior to reflow (figs. 2A-2B).
Regarding claim 13, Lu discloses further including singulating the substrate, wherein the singulation removes the SMA structure (figs. 7C-7D).
Regarding claim 14, Lu, in figs. 2A-2B, discloses a method of making a semiconductor device, comprising: providing a semiconductor die 100; disposing a shape-metal alloy (SMA) structure 206 over the semiconductor die 100; disposing the semiconductor die 100 over a substrate 106 with the SMA structure 206 between the semiconductor die 100 and substrate 106.
Lu discloses a method of making a semiconductor device as above but fails to disclose the semiconductor die is an interposer die.
However, Chen discloses the semiconductor die 101 is an interposer die (fig.1 & [0023]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the interposer die as taught by Chen in order to provide support and connectivity for electronic components and devices mounted thereon.
Regarding claim 15, Chen discloses further including disposing a semiconductor package 102 over the interposer 101 opposite the substrate 106 with a solder bump 103/104 of the semiconductor package 102 disposed between the semiconductor package 102 and interposer 101 (fig. 1).
Regarding claim 16, Chen discloses further including reflowing the solder bump 107 after disposing the semiconductor package 102 over the interposer 101 (fig. 8B).
Regarding claim 17, Lu discloses wherein reflowing the solder bump 114 expands the SMA structure 206 (fig. 2B).
Regarding claim 18, Lu discloses wherein the SMA structure shrinks while cooling after reflow (fig. 2B).
Regarding claim 19, Chen discloses further including disposing a plurality of SMA structures 107 over the interposer 101 with one of the plurality of SMA structures 107 disposed at each corner of the interposer 101 (fig. 8E).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
