Prosecution Insights
Last updated: October 27, 2026

David Vu, USPTO Patent Examiner

Listed by the USPTO as VU, DAVID

Tech Center 2800 • Art Units: 2818

This examiner grants 77% of resolved cases

Analysis

VU, DAVID is assigned to Tech Center 2800 and Art Unit 2818. The profile covers 754 resolved cases, with a 77.3% allowance rate and a median of 1016 days to allowance. Interviews show an 18.0% lift, making them a useful option when written claim arguments would benefit from direct discussion.

Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and NANYA TECHNOLOGY Corporation are the leading companies. The listed firms are Harrity & Harrity, LLP, IntelliFluence Patent Firm, and JCIPRNET. The substantial record supports structured planning around semiconductor claim scope, response timing, and selective examiner engagement.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

77.3%
Allow Rate
+9.3% vs TC avg
774
Total Applications
+18.0%
Interview Lift
1016
Avg Prosecution Days
Based on 754 resolved cases, 2023–2026

Rejection Statute Breakdown

0.8%
§101 Eligibility
33.0%
§102 Novelty
54.9%
§103 Obviousness
8.7%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18808369 SEMICONDUCTOR DEVICE Non-Final OA Samsung Electronics Co., Ltd.
18214271 CONDUCTIVE LINES HAVING MOLYBDENUM LINER AND TUNGSTEN FILL FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Non-Final OA Intel Corporation
18688326 SEMICONDUCTOR-SUPERCONDUCTOR HYBRID DEVICE HAVING A TUNNEL BARRIER Non-Final OA Microsoft Technology Licensing LLC
18783486 IMPLANTATION MASK FORMATION Non-Final OA Taiwan Semiconductor Manufacturing Company , Ltd.
18779252 STILTED PAD STRUCTURE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18634774 SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18786948 CAVITY RESONATOR FOR ENHANCING RADIO-FREQUENCY PERFORMANCE AND METHODS FOR FORMING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Company Limited
18739609 MEMORY DEVICE INCLUDING WORD LINE STRUCTURE HAVING LOWER AND UPPER GATE ELECTRODE LAYERS AND METHOD FOR PREPARING THE SAME Final Rejection NANYA TECHNOLOGY CORPORATION
18655444 MEMORY DEVICE INCLUDING WORD LINE STRUCTURE HAVING LOWER AND UPPER GATE ELECTRODE LAYERS AND METHOD FOR PREPARING THE SAME Final Rejection NANYA TECHNOLOGY CORPORATION

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Frequently Asked Questions

What is examiner David Vu's allowance rate?

77.3% of resolved applications examined by David Vu were allowed (754 resolved cases), compared with 85.2% across Art Unit 2818 over the last five years.

Does an interview help with examiner David Vu?

This examiner's interview lift is +18.0 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner David Vu take to allow a patent?

Applications allowed by David Vu took 1,016 days on average from filing to allowance.

Which art unit does examiner David Vu work in?

David Vu examines applications in Art Unit 2818 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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