DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-7, 9-12, 15-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2022/0359358 to Kim (hereinafter Kim).
Regarding Claim 1, Kim discloses an electronic package, comprising:
a carrier structure (250, Fig. 2) having a first side and a second side opposing the first side, wherein the first side is formed with a plurality of conductive pillars (415) electrically connected to the carrier structure;
a plurality of first electronic elements (350) bonded on and electrically connected to the first side of the carrier structure (Fig. 2);
a second electronic element (340) bonded onto the plurality of first electronic elements (Fig. 2);
an encapsulating layer (460) formed on the first side of the carrier structure and covering the plurality of first electronic elements, the second electronic element and the plurality of conductive pillars; and
a circuit structure (200) formed on the encapsulating layer and electrically connected to the plurality of conductive pillars and the second electronic element (Fig. 2).
Regarding Claim 2, Kim discloses the electronic package of Claim 1, wherein each of the plurality of first electronic elements has an active surface and an inactive surface opposing the active surface, and the plurality of first electronic elements are all connected to the carrier structure via the active surfaces thereof (Fig. 2).
Regarding Claim 5, Kim discloses the electronic package of Claim 1, wherein the plurality of first electronic elements are electrically connected to the carrier structure in a flip-chip manner or a wire-bonding manner (Fig. 2).
Regarding Claim 6, Kim discloses the electronic package of Claim 1, wherein the second electronic element is disposed on the plurality of first electronic elements via a bonding layer (450).
Regarding Claim 7, Kim discloses the electronic package of Claim 1, wherein the second electronic element has an active surface and an inactive surface opposing the active surface, and a plurality of conductive bumps (342) are formed on the active surface and electrically connected to the circuit structure.
Regarding Claim 9, Kim discloses the electronic package of Claim 1, further comprising a plurality of solder balls formed on the second side of the carrier structure (Fig. 2).
Regarding Claim 10, Kim discloses the electronic package of Claim 1, further comprising a plurality of conductive elements (335) formed on the circuit structure (Fig. 2).
Regarding Claim 11, Kim discloses a method of manufacturing an electronic package, comprising:
providing a carrier structure (250, Fig. 2) having a first side and a second side opposing the first side, wherein the first side is formed with a plurality of conductive pillars (415) electrically connected to the carrier structure;
disposing an electronic element stacking structure on the first side of the carrier structure, wherein the electronic element stacking structure comprises a plurality of first electronic elements (350) bonded and electrically connected to the carrier structure and a second electronic element (340) bonded to the plurality of first electronic elements;
forming an encapsulating layer (460) on the first side of the carrier structure to cover the electronic element stacking structure and the plurality of conductive pillars, wherein end surfaces of the plurality of conductive pillars and the second electronic element are exposed from the encapsulating layer (Fig. 2); and
forming a circuit structure (200) on the encapsulating layer, wherein the circuit structure is electrically connected to the plurality of conductive pillars and the second electronic element (Fig. 2).
Regarding Claim 12, Kim discloses the method of Claim 11, wherein each of the plurality of first electronic elements has an active surface and an inactive surface opposing the active surface, and the plurality of first electronic elements are all connected to the carrier structure via the active surfaces thereof (Fig. 2).
Regarding Claim 15, Kim discloses the method of Claim 11, wherein the plurality of first electronic elements are electrically connected to the carrier structure in a flip-chip manner or a wire-bonding manner (Fig. 2).
Regarding Claim 16, Kim discloses the method of Claim 11, wherein the second electronic element is disposed on the plurality of first electronic elements via a bonding layer (450).
Regarding Claim 17, Kim discloses the method of Claim 11, wherein the second electronic element has an active surface and an inactive surface opposing the active surface, and a plurality of conductive bumps (342) are formed on the active surface and electrically connected to the circuit structure.
Regarding Claim 19, Kim discloses the method of Claim 11, further comprising forming a plurality of solder balls (150) on the second side of the carrier structure (Fig. 2).
Regarding Claim 20, Kim discloses the method of Claim 11, further comprising forming a plurality of conductive elements (335) on the circuit structure (200).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 8, 13, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to Claims 1 and 11 above, and further in view of US PG Pub 2017/0345761 to Yu et al (hereinafter Yu).
Regarding Claims 3, 4, 13 and 14, Kim discloses the electronic package of Claim 1 and method of Claim 11, wherein each of the plurality of first electronic elements has an active surface and an inactive surface opposing the active surface, but does not disclose the plurality of first electronic elements all being connected to the carrier structure via the inactive surfaces thereof.
Yu discloses an electronic package (Fig. 2) having first electronic elements (120) attached to a carrier structure (200, Fig. 3D) via the electronic elements inactive surfaces.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the first electronic elements of Kim to be attached to the carrier by way of their inactive surfaces to provide an active surface for upper levels of metallization and circuit building. Similarly, it would have been an obvious design choice to have one first electronic element attached to the carrier by it’s active surface and the other by it’s inactive surface based on design goals and circuit construction.
Regarding Claims 8 and 18, Kim discloses the electronic package of Claim 1 and method of Claim 11 but does not disclose wherein a width of the second electronic element is less than an overall layout width of the plurality of first electronic elements.
Yu discloses an electronic package (Fig. 4) having a second electronic element (130) over first electronic elements (11) wherein a width of the second electronic element is less than an overall layout width of the plurality of first electronic elements (Fig. 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the second electronic element of Kim to have a width less than an overall layout width of the plurality of first electronic elements. Electronic elements come in various widths based on their function and the package design goals and would have been an obvious design choice.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
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