Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 05/29/2023.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/22/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim(s) 5 and 12 recite the limitation "the primary heat sink base partially extends to a position above the top surface of the auxiliary semiconductor die" in lines 2-3 of each claim. However, claims 4 and 11, which claims 5 and 12 depend on, respectively, recite “a bottom surface of the primary heat sink partially extends to a position above the top surface of the auxiliary second semiconductor die”. It is unclear if the recitation of “a position” in claims 5 and 12 is referring to the same position as claims 4 and 11 (and should be “the position”) or if the recitation of “a position” in claims 5 and 12 is referring to a different position (and should be “a second position”). Therefore, claims 5 and 12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, the above limitation in claims 5 and 12 will be interpreted to read as “the primary heat sink base partially extends to a second position above the top surface of the auxiliary semiconductor die”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0407879 A1; Patel et al.; 12/2021; (“Patel”).
Regarding Claim 1. Patel discloses A semiconductor package (#400, Figure 4, multi-chip module), comprising:
a primary semiconductor die (#104, Figure 4, substrate which may be made of silicon and include various elements according to [0019] such that it may be interpreted as a semiconductor die) with a top surface (Figure 4, top surface of #104), wherein the top surface comprises a first region (Figure 4, central region where #148 is mounted) and a second region besides the first region (Figure 4, left region where #140 is mounted which is beside the region where #148 is mounted);
an auxiliary semiconductor die (#148, Figure 4, fifth IC chip) attached on the first region of the top surface of the primary semiconductor die (Figure 4, #148 is attached to the central region of the top surface of #104);
a primary heat spreader assembly (#444/#436, Figure 4, heat conducting structure and heat sink) attached on the second region of the top surface of the primary semiconductor die (Figure 4, the combination of #444 and #436 are attached on the left side surface of #104); and
an auxiliary heat spreader assembly (#416, Figure 4, heat sink on #148) attached on a top surface of the auxiliary semiconductor die (Figure 4, #416 is attached on a top surface of #148), wherein the primary heat spreader assembly is thermally isolated from the auxiliary heat spreader assembly (Figure 4, #416 and #444/#436 are thermally isolated by air gaps therebetween with the only attachments being small screws which is in agreement with [0022] of the instant application, “although the primary heat spreader assembly 130 and the auxiliary heat spreader assembly 140 are designed to be thermally isolated, they may be structurally connected . . . For example, the primary heat spreader assembly 130 and the auxiliary heat spreader assembly 140 may be structurally connected via thin connection rods”).
Regarding Claim 2. Patel discloses The semiconductor package of claim 1, wherein the primary heat spreader assembly partially extends from the second region of the top surface of the primary semiconductor die to a position above the top surface of the auxiliary semiconductor die (Figure 4, the combination of #444 and #436 extends from the left region of the top surface of #104 to a position above the top surface of #148).
Regarding Claim 3. Patel discloses The semiconductor package of claim 1, wherein the primary heat spreader assembly comprises:
a primary intermediate block (Figure 4, non-numbered thermal interface material, TIM, on top of #140, see Figure 2, that may be interpreted as part of the primary heat spreader assembly) attached on the second region of the top surface of the primary semiconductor die (Figure 4, the TIM on #140 is attached on the left region of the top surface of #104 where “attached” does not require direct contact according to [0018] of the instant application); and
a primary heat sink (#436, Figure 4, heat sink) attached on a top surface of the primary intermediate block (Figure 4, #436 is attached on a top surface of the TIM on #140).
Regarding Claim 4. Patel discloses The semiconductor package of claim 3, wherein the top surface of the primary intermediate block levels with the top surface of the auxiliary semiconductor die (Figure 4, the top surface of the TIM on #140 levels with the top surface of #148); and
a bottom surface of the primary heat sink partially extends to a position above the top surface of the auxiliary semiconductor die (Figure 4, a bottom surface of #436 extends to a plurality of point positions above the top surface of #148).
Regarding Claim 5. Patel discloses The semiconductor package of claim 4, wherein the primary heat sink (#436) comprises:
a primary heat sink base (Figure 4, horizontally extending portion of #436), wherein the primary heat sink base partially extends to a second position above the top surface of the auxiliary semiconductor die (Figure 4, the horizontally extending portion of #436 extends to a plurality of point positions above the top surface of #148); and
a set of primary heat sink fins extending from the primary heat sink base (Figure 4, the plurality of vertically extending portions, or fins, extending from the top surface of the horizontally extending portion).
Regarding Claim 6. Patel discloses The semiconductor package of claim 1, wherein the primary heat spreader assembly (#444/#436) is attached on the top surface of the primary semiconductor die (#104) via an adhesion layer (Figure 4, solder balls between #140 and #104) and a thermal interface material layer (Figure 4, non-numbered TIM on #140) on the adhesion layer (Figure 4, #444 is at least partially attached to the top surface of #104 through the solder balls and the TIM which is on the solder balls where “on” does not require direct contact according to [0018] of the instant application), and
the auxiliary heat spreader assembly (#416) is attached to the auxiliary semiconductor die via an adhesion layer (non-numbered stiffener ring, Figure 4, see Figure 2) and a thermal interface material layer (non-numbered TIM on #148, Figure 4, see Figure 2) (Figure 4, #416 is at least partially attached to #104 though the non-numbered TIM on #148 and the stiffener ring on the edge of #104).
Regarding Claim 7. Patel discloses The semiconductor package of claim 1, wherein the auxiliary heat spreader assembly comprises:
an auxiliary intermediate block (Figure 4, non-numbered thermal interface material, TIM, on top of #148, see Figure 2, that may be interpreted as part of the auxiliary heat spreader assembly) attached on the top surface of the auxiliary semiconductor die (Figure 4, the non-numbered TIM on #148 is attached to a top surface of #148); and
an auxiliary heat sink attached on a top surface of the auxiliary intermediate block, comprising a set of auxiliary heat sink fins (#416, Figure 4, #416 is attached on a top surface of the TIM and comprises a plurality of vertically extending fins).
Regarding Claim 8. Patel discloses A method (Figure 8) for forming a semiconductor package (#400, Figure 4, multi-chip module), comprising:
providing a semiconductor die stack (Figure 4, a plurality of dies are stacked) with a primary semiconductor die (#104, Figure 4, substrate which may be made of silicon and include various elements according to [0019] such that it may be interpreted as a semiconductor die) and an auxiliary semiconductor die (#148, Figure 4, fifth IC chip),
wherein the primary semiconductor die comprises a top surface (Figure 4, top surface of #104) comprising a first region (Figure 4, central region where #148 is mounted) and a second region besides the first region (Figure 4, left region where #140 is mounted which is beside the region where #148 is mounted),
wherein the auxiliary semiconductor die is attached onto the first region of the top surface of the primary semiconductor die (Figure 4, #148 is attached to the central region of the top surface of #104);
attaching a primary heat spreader assembly (#444/#436, Figure 4, heat conducting structure and heat sink) on the second region of the top surface of the primary semiconductor die (Figure 4, the combination of #444 and #436 are attached on the left side surface of #104); and
attaching an auxiliary heat spreader assembly (#416, Figure 4, heat sink on #148) on a top surface of the auxiliary semiconductor die (Figure 4, #416 is attached on a top surface of #148),
wherein the primary heat spreader assembly is thermally isolated from the auxiliary heat spreader assembly (Figure 4, #416 and #444/#436 are thermally isolated by air gaps therebetween with the only attachments being small screws which is in agreement with [0022] of the instant application, “although the primary heat spreader assembly 130 and the auxiliary heat spreader assembly 140 are designed to be thermally isolated, they may be structurally connected . . . For example, the primary heat spreader assembly 130 and the auxiliary heat spreader assembly 140 may be structurally connected via thin connection rods”).
Regarding Claim 9. Patel discloses The method of claim 8, wherein upon attaching a primary heat spreader assembly, the primary heat spreader assembly partially extends from the second region of the top surface of the primary semiconductor die to a position above the top surface of the auxiliary semiconductor die (Figure 4, the combination of #444 and #436 extends from the left region of the top surface of #104 to a position above the top surface of #148).
Regarding Claim 10. Patel discloses The method of claim 8, wherein attaching a primary heat spreader assembly comprises:
attaching a primary intermediate block (Figure 4, non-numbered thermal interface material, TIM, on top of #140, see Figure 2, that may be interpreted as part of the primary heat spreader assembly) on the second region of the top surface of the primary semiconductor die (Figure 4, the TIM on #140 is attached on the left region of the top surface of #104 where “attached” does not require direct contact according to [0018] of the instant application); and
attaching a primary heat sink (#436, Figure 4, heat sink) on a top surface of the primary intermediate block (Figure 4, #436 is attached on a top surface of the TIM on #140).
Regarding Claim 11. Patel discloses The method of claim 10, wherein upon attaching a primary intermediate block, the top surface of the primary intermediate block levels with the top surface of the auxiliary semiconductor die (Figure 4, the top surface of the TIM on #140 levels with the top surface of #148); and
upon attaching a primary heat sink, a bottom surface of the primary heat sink partially extends to a position above the top surface of the auxiliary semiconductor die (Figure 4, a bottom surface of #436 extends to a plurality of point positions above the top surface of #148).
Regarding Claim 5. Patel discloses The method of claim 11, wherein attaching a primary heat sink comprises:
attaching a primary heat sink base (Figure 4, horizontally extending portion of #436), wherein the primary heat sink base partially extends to a second position above the top surface of the auxiliary semiconductor die (Figure 4, the horizontally extending portion of #436 extends to a plurality of point positions above the top surface of #148); and
attaching a set of primary heat sink fins extending from the primary heat sink base (Figure 4, the plurality of vertically extending portions, or fins, extending from the top surface of the horizontally extending portion).
Regarding Claim 13. Patel discloses The method of claim 8, wherein attaching a primary heat spreader assembly comprises:
forming an adhesion layer (Figure 4, solder balls between #140 and #104) and a thermal interface material layer (Figure 4, non-numbered TIM on #140); and
wherein attaching an auxiliary heat spreader assembly comprises:
forming an adhesion layer (non-numbered stiffener ring, Figure 4, see Figure 2) and a thermal interface material layer (non-numbered TIM on #148, Figure 4, see Figure 2).
Regarding Claim 14. Patel discloses The method of claim 8, wherein attaching an auxiliary heat spreader assembly comprises:
attaching an auxiliary intermediate block (Figure 4, non-numbered thermal interface material, TIM, on top of #148, see Figure 2, that may be interpreted as part of the auxiliary heat spreader assembly) on the top surface of the auxiliary semiconductor die (Figure 4, the non-numbered TIM on #148 is attached to a top surface of #148); and
attaching an auxiliary heat sink on a top surface of the auxiliary intermediate block, wherein the auxiliary heat sink comprises a set of auxiliary heat sink fins (#416, Figure 4, #416 is attached on a top surface of the TIM and comprises a plurality of vertically extending fins).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0155218 A1; Hung et al.; 06/2015 – Figure 1J discloses a 3DIC package including a stack of two semiconductor dies (#10/#12) with a primary heat spreader (#30) attached to the lower semiconductor die (#12) through a thermal interface material (#24b) and an auxiliary heat spreader (#34) attached to the upper semiconductor die (#10) through a thermal interface material (#24a) wherein the primary and secondary heat spreaders are thermally isolated from one another by adhesives (#32, Figure 1I) and air gaps.
US 9,082,743 B2; Hung et al.; 07/2015 – Figure 15A discloses a 3DIC package including a stack of two semiconductor dies (#10/#12) with a primary heat spreader (#20) attached to the lower semiconductor die (#12) through a thermal interface material (#16B) and an auxiliary heat spreader (#24) attached to the upper semiconductor die (#10) through a thermal interface material (#16A) wherein the primary and secondary heat spreaders are thermally isolated from one another by adhesives (#26) and air gaps.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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