DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 8/1/26 have been fully considered but they are not persuasive.
Applicant argues the combination of references fails to teach the distribution density as provided in amended claim 1. In response, Or-Bach ‘531 teaches concentrating thermal vias in a center region relative to a peripheral region. Applying that known distribution to the heat sink arrangement of Uzoh would predictably increase thermal transfer capacity in the region of greater heat generation while retaining a lower peripheral via density.
Applicant argues the combination of references fails to teach the distribution density as provided in amended claim 6. In response, the existing rejection of claim 6 is sustainable combined with the teaching in Or-Bach ‘531 of the thermal via distribution in the center and peripheral regions that correspond to claim 1.
Applicant’s arguments with respect to claim(s) 7, 8, 12 have been considered but are moot because the new ground of rejection rely on new references for teaching matters specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 6, 11, 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2024/0203823 (Uzoh) in view of TW Publication No. 2024-03962 (Wang) and U.S. Patent No. 9,640,531 (Or-Bach ‘531).
Uzoh discloses
1. (Currently amended) A package structure, comprising:
an electronic device 102; and
a heat sink structure 108 disposed over the electronic device 102, and comprising:
a base portion (bottom);
a plurality of thermal vias 114; and
a thermally conductive layer 110 connecting to the plurality of thermal vias 114, wherein the plurality of thermal vias 114 are thermally connected to the electronic device 102 through the thermally conductive layer 110 so as to dissipate a heat generated from the electronic device 102 ([0044]-[0046]).
Uzoh fails to disclose
a heat sink structure comprising:
a base portion;
a plurality of thermal vias extending through the base portion;
a thermally conductive layer having a center portion and a peripheral portion, embedded in the base portion,
wherein the thermal vias are distributed at the center portion and the peripheral portion of the thermally conductive layer that a distribution density of the thermal vias at the center portion of the thermally conductive layer is greater than a distribution density of the thermal vias at the 15 peripheral portion of the thermally conductive layer.
Wang teaches
A package structure, comprising:
a heat sink structure (at least Figure 2B), comprising:
a base portion 52;
a plurality of thermal vias (unlabeled area including T1 / T2) extending through the base portion 52;
a thermally conductive layer 66 having a center portion 65C and a peripheral portion 65A embedded in the base portion 52.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the heat sink structure of Uzoh. The motivation would be to provide an enhanced thermal conduction path within the heat sink body, improve heat spreading from localized heat sources, and improve thermal transfer efficiency between the electronic device and the heat sink structure as taught by Wang.
Bach ‘531 teaches
A package structure, comprising:
wherein the thermal vias 444-447 are distributed at the center portion and the peripheral portion such that a distribution density of the thermal vias 444-445 at the center portion is greater than a distribution density of the thermal vias 446-447 at the peripheral portion.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the heat sink structure of Uzoh. The motivation would be a matter of routine engineering considerations to optimize the distribution of the thermal vias in the heat sink structure to provide increased thermal conduction in a region having a greater thermal load as taught by Or-Bach ‘531 (col. 15, line 5 to col. 17, line 6). See MPEP 2144.04.
Wang teaches
2. The package structure of Claim 1, wherein the heat sink structure (at least Fig. 9) is attached to the electronic device by hybrid bonding.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use hybrid bonding in Uzoh. The motivation would be to reduce thermal interference resistance, improve thermal conductivity between the electronic device and the heat sink structure, and provide a direct thermal conduction path as taught by Wang.
Or-Bach ‘531 teaches
6. (Currently amended) The package structure of Claim 1, wherein the plurality of thermal vias 444-447 include a plurality of first thermal vias 444/445 distributing at the center portion of the thermally conductive layer (Wang) and a plurality of second thermal vias 446/447 distributing at the peripheral portion of the thermally conductive layer (Wang) and surrounding the plurality of first thermal vias 444/445, wherein a distribution density of the plurality of first thermal vias is greater than a distribution density of the plurality of second thermal vias (column 15, line 5 to column 16, line 52).
Wang teaches
11. The package structure of Claim 1, wherein the heat sink structure (at least Fig. 5) further comprises a dielectric layer 56 / 62 disposed on a first surface of the base portion 52, and surrounding the thermally conductive layer 66.
Uzoh discloses ([0044])
13. The package structure of Claim 1, wherein the plurality of thermal vias 114 and the thermally conductive layer 110 are formed concurrently and integrally.
Wang teaches
14. The package structure of Claim 1, wherein the electronic device comprises:
a first semiconductor chip 150; and
an encapsulant 200 encapsulating the first semiconductor chip 150, wherein the thermally conductive layer 66 of the heat sink structure vertically overlaps the encapsulant 200 of the electronic device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an encapsulant in Uzoh. The motivation would be an encapsulant is well-known in the package art as shown in Wang. See MPEP 2144.03.
Wang teaches
15. The package structure of Claim 14, wherein a lateral surface of the base portion 52 of the heat sink structure is substantially aligned with a lateral surface of the encapsulant 200 of the electronic device.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in view of Wang and Or-Bach ‘531 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2021/0233901 (Or-Bach ‘901).
The combination of references fails to teach
3. The package structure of Claim 1, wherein the thermally conductive layer has a net shape.
Or-Bach ‘901 teaches (at least Figs. 9A, 9B, 11A-11K, 12A-12J)
A package structure, comprising:
wherein the thermally conductive layer 1157 has a net shape.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to determine the optimal shape in the modified device of Uzoh. The motivation would be to provide thermal isolation as taught by Or-Bach ‘901. See MPEP 2144.04.
Or-Bach ‘901 teaches
4. The package structure of Claim 3, wherein the thermally conductive layer 1157 includes a plurality of lines crossed with each other to form a plurality of intersection portions.
Or-Bach ‘901 teaches ([0114], [0115])
5. The package structure of Claim 4, wherein the plurality of thermal vias are connected to the plurality of intersection portions of the thermally conductive layer 1157.
Claim(s) 7, 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in view of Wang and Or-Bach ‘531 as applied to claim 1 above, and further in view of U.S. Patent No. 7,768,122 (Oda) and U.S. Patent Application Publication No. 2024/0332239 (Polomoff).
The combination of references fails to teach
7. (Currently amended) The package structure of Claim 1, wherein the heat sink structure further comprises a plurality of conductive elements covering the plurality of thermal vias, wherein each of the conductive elements has a hemisphere shape enclosing the thermal vias therewithin.
Oda teaches
A package structure, comprising:
wherein the heat sink structure (Fig. 2) further comprises a plurality of conductive elements 12 / 22 covering the plurality of thermal vias 11 / 21.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide conductive elements in the modified device of Uzoh. The motivation would be to provide a continuous, low-resistance thermal path directly to the heat sink. This prevents solder wicking, protects the vias from contaminants, and ensures structural consistency as taught by Oda.
Polomoff teaches (at least Figs. 7E, 7F)
A package structure, comprising:
wherein each of the conductive elements 709 has a hemisphere shape enclosing the thermal vias 706, 707 therewithin.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide conductive elements covering the thermal vias in the modified device of Uzoh. The motivation would be to allow for direct paths through the hierarchy of a 3D architecture to thereby provide faster and shorter direct power distribution paths along with increased heat dissipation as taught by Polomoff ([0022]).
Wang teaches
9. The package structure of Claim 7, wherein the heat sink structure (at least Fig. 4) further comprises a protection material 80 disposed on a second surface of the base portion 52, and encapsulating the plurality of conductive elements 72 / 76.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a protection material in the modified device of Uzoh. The motivation would be to protect the underlying features from harmful chemicals and moisture during subsequent processing as taught by Wang.
Uzoh discloses (at least Fig. 4)
10. The package structure of Claim 9, wherein a top surface of one of the plurality of conductive elements 316 / 412 / 424 is exposed by the protection material 104, and a lateral surface of one of the plurality of conductive elements 316 / 412 / 424 includes a curved surface.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in view of Wang and Or-Bach ‘531, Oda, and Polomoff as applied to claim 7 above, and further in view of U.S. Patent Application Publication No. 2016/0155715 (Lin).
The combination of references fails to teach
8. (Currently amended) The package structure of Claim 7, wherein the plurality of conductive elements include a center conductive element enclosing the thermal vias at the center portion of the thermally conductive layer and a periphery conductive element enclosing the thermal vias at the peripheral portion of the thermally conductive layer, and a height of the center conductive element is greater than a height of the periphery conductive element.
Lin teaches (at least Figs. 3A, 3B)
A package structure comprising:
wherein the plurality of conductive elements 103c, 103p include a center conductive element 103c enclosing the thermal vias (Polomoff) at the center portion 111 of the thermally conductive layer (Wang) and a periphery conductive element 103p enclosing the thermal vias (Polomoff) at the peripheral portion 112 of the thermally conductive layer (Wang), and a height of the center conductive element 103c is greater than a height of the periphery conductive element 103p.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the center conductive element with a greater height than the periphery conductive element in the modified device of Uzoh. The motivation would be to accommodate differences in spacing between the center and peripheral regions, provide reliable conductive connection, and avoid a cold joint as taught by Lin ([0034]-[0038], [0048]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in view of Wang and Or-Bach ‘531 as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2022/0068817 (Li).
Wang teaches
12. (Currently amended) The package structure of Claim 1, wherein a material of the base portion 52 includes silicon, and the thermally conductive layer 66 includes a conductive material 65C and a barrier layer 65B disposed between the conductive material 65C and the base portion 52;
The combination of references fails to teach
wherein the base portion has a recess and a plurality of holes formed in the recess, wherein the thermal vias are formed in the holes within the recess of the base portion.
Li teaches
A package structure comprising:
wherein the base portion 110 has a recess 120 and a plurality of holes 114 formed in the recess 120, wherein the thermal vias ([0041]-[0046]) are formed in the holes 114 within the recess 120 of the base portion 110.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a recess having holes that are thermal vias in the base portion in the modified device of Uzoh. The motivation would be to help ensure coplanarity of the top ends of the thermal vias with the mounting surface, the size and thickness of the metal thermal dissipation structures may be adjusted based on cost and heat dissipation objectives among other factors, and low-temperature sintering processes may reduce warping of the substrate or PCB that may otherwise occur when higher-temperature processes are used as taught by Li ([0038]).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in view of Wang as applied to claim 14 above, and further in view of U.S. Patent Application Publication No. 2023/0078980 (Choi).
The combination of references fails to teach
16. The package structure of Claim 14, wherein the electronic device further comprises:
a second semiconductor chip stacked on and electrically connected to the first semiconductor chip;
wherein the encapsulant further encapsulates the second semiconductor chip.
Choi teaches
A package structure, comprising:
wherein the electronic device further comprises:
a second semiconductor chip 330 stacked on and electrically connected to the first semiconductor chip 320;
wherein the encapsulant 350 further encapsulates the second semiconductor chip 330.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to stack chips in the modified device of Uzoh. The motivation would be stacked chips are well-known in the package art as taught by Choi. See MPEP 2144.03.
Choi teaches
17. The package structure of Claim 16, wherein a bottom surface of the second semiconductor chip 330 contacts a top surface of the first semiconductor chip 320.
It would have been obvious to a person of ordinary skill in the art to provide additional stacked chips in the modified device of Uzoh based on their suitability for the intended purpose. See MPEP 2144.07.
18. The package structure of Claim 16, wherein the electronic device further comprises:
a third semiconductor chip stacked on and electrically connected to the second semiconductor chip;
wherein the encapsulant further encapsulates the third semiconductor chip.
It would have been obvious to a person of ordinary skill in the art to provide additional stacked chips in the modified device of Uzoh based on their suitability for the intended purpose. See MPEP 2144.07.
19. The package structure of Claim 18, wherein a bottom surface of the third semiconductor chip contacts a top surface of the second semiconductor chip.
It would have been obvious to a person of ordinary skill in the art to provide additional stacked chips in the modified device of Uzoh based on their suitability for the intended purpose. See MPEP 2144.07.
20. The package structure of Claim 18, wherein the electronic device further comprises:
a fourth semiconductor chip stacked on and electrically connected to the third semiconductor chip; wherein the encapsulant further encapsulates the fourth semiconductor chip.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2013/0082372 (Lin), 2023/0078980 (Choi), 2024/0128150 (Tong) teach a semiconductor package having a heat sink structure directly over the electronic device and uses an embedded thermally conductive layer to bridge the device and multiple thermal vias.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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