DETAILED ACTION
This correspondence is in response to the communications received August 13, 2026. Claims 9-28 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II in the reply filed on August 13, 2026 is acknowledged.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 9, the Applicant discloses in Figs. 3F-3G, a method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer (62, ¶ 0037) over a channel region (upper portion of fin 20 under gate);
forming a first conductive layer (“first conductive layer 63”, ¶ 0044) over the gate dielectric layer (over 62);
forming a second conductive layer (“second conductive layer 65”, ¶ 0045) over the first conductive layer (65 over 63);
forming a protective layer (“protective layer 66”, ¶ 0045) at a surface region of the second conductive layer (66 formed at the surface of 65, “the protective layer 66 is a modified surface region of the second conductive layer 65”, ¶ 0045) by implanting a dopant into the surface region of the second conductive layer (“In some embodiments, the B2H6 gas is applied to the surface of the TaN 65 for 1 sec to 60 sec.”, ¶ 0046),
wherein the dopant is selected from the group consisting of boron, silicon, carbon, and nitrogen (“In some embodiments, the B2H6 gas is applied to the surface of the TaN 65 for 1 sec to 60 sec.”, ¶ 0046);
forming a metallic layer by using a metal containing gas over the protective layer (“a third conductive layer 67 is formed over the protective layer 66 … the third … conductive layers are metallic layers. In some embodiments, the third conductive layer 67 is a W (tungsten) layer”, ¶ 0047); and
removing the metallic layer by a wet etching operation using a solution containing H3PO4 (“Then, as shown in FIG. 3G, at operation 255 of FIG. 1B, the TiN layer 68 and the W layer 67 are removed. In some embodiments, the TiN layer 68 and the W layer 67 are removed by an aqueous solution containing H3PO4, H2O2 and H2O. Due to the protective layer 66, a chemical reaction and/or physical interaction between the TaN layer 65 and the W layer is suppressed, and the aqueous solution does not cause damage to the TaN layer 65.”, ¶ 0050).
Double Patenting
A non-statutory double patenting rejection with regard to the parent application 17/379,431 now (US 12,020,947) was considered, however the claims are directed only to structure claims.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9-17 and 21-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-13 and 15-19 of U.S. Patent No. 11,069,534 in view of Foord et al. (US 2015/0348752), Ogawa (US 2009/0146215), Lee et al. (US 2019/0333915), Savant et al. (US 2020/0135915), respectively.
Although the claims at issue are not identical, they are not patentably distinct from each other because the parent application contains each of the instant application’s claimed limitations.
It is noted here, that the repetition of the claim language in the following rejections will be included only when it is not readily apparent how the claims share similar limitations or when obviousness type rejection is required. When claim numbers are only stated, it should be readily apparent to the reader, which limitations are shared by the instant application and the parent application.
Claim limitation(s) of the instant application (IA)
Claim limitation(s) of the (US 11,069,534) patent
9. A method of manufacturing a semiconductor device, comprising:
A forming a gate dielectric layer over a channel region;
B forming a first conductive layer over the gate dielectric layer;
C forming a second conductive layer over the first conductive layer;
D forming a protective layer at a surface region of the second conductive layer D1 by implanting a dopant into the surface region of the second conductive layer,
D2 wherein the dopant is selected from the group consisting of boron, silicon, carbon, and nitrogen;
E forming a metallic layer by using a metal containing gas over the protective layer; and
F removing the metallic layer by a wet etching operation using a solution containing H3PO4.
11. A method of manufacturing a semiconductor device including a field effect transistor, comprising:
A forming a gate dielectric layer over a channel region;
B forming a first conductive layer over the gate dielectric layer;
C forming a second conductive layer over the first conductive layer;
D forming a protective layer on a surface or at a surface region of the second conductive layer;
E forming a metallic layer by using a metal containing gas over the protective layer; and
F removing the metallic layer by a wet etching operation using a solution containing H.sub.3PO.sub.4,
wherein the protective layer protects the second conductive layer from the solution of the wet etching operation so that the protective layer remains at an end of the wet etching operation.
The 534’ patent claims do not disclose wherein the dopants are introduced into the second conductive layer by implantation process. However, the second conductive layer is doped by gas application, see claim 13. So the type of dopant introduction process is merely lacking. Foord discloses in ¶ 0037, “The hardening process is not limited to beryllium ions and other ions can be used to provide a similar effect. For example, Li.sup.+, Mg.sup.+, and Ca.sup.+may be useful to implant into Si or other materials. Other material that may be useful for implanting to harden a material include Ga.sup.+, Xe.sup.+, Ar.sup.+, O.sup.+, In.sup.+, Si.sup.+, Kr.sup.+, and Bi.sup.+. Implanting may be useful to harden almost any material, but the process may be particularly useful in applications that harden silicon, silicon nitride, silicon carbide, tungsten, SiGe, low-k dielectric materials (“carbon-doped oxide”), tantalum, tantalum nitride, titanium, titanium nitride, aluminum.” This teaching shows the process of hardening material layers with implantation of ion species to modify the etch rate (see title) of the material films. One material film noted is “tantalum nitride” and one of the type of implantable dopant species is silicon.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the D1 “by implanting a dopant into the surface region of the second conductive layer”, as disclosed by Foord in the system of ‘534 patent, for the purpose of utilizing a method of doping which can accurately deliver dopants at the desired material layer depth and quantity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
As the ‘534 patent already shows the other dopant species in claim 13, the only missing piece of D1 and D2, was the implantation process. See claim 13 which shows dopant species introduced by doping into the second conductive layer.
D2 13. The method of claim 11, wherein the protective layer is formed by applying a gas containing one element selected from the group consisting of B, N, C, and Si to a surface of the second conductive layer.
10. (Currently Amended) The method of claim 9, wherein a thickness of the protective layer is in a range from 1 nm to 10 nm.
The ‘534 patent does not disclose the content of claim 10. However Ogawa discloses a tantalum nitride film for use as a barrier layer in a gate electrode is 1 nm in thickness, see ¶ 0028, “The second gate electrode 14B includes a second conductive film 32 made of tantalum nitride (TaN) having a thickness of 5 nm”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a thickness of the protective layer is in a range from 1 nm to 10 nm”, as disclosed by Ogawa in the system of ‘534 patent, for the purpose of utilizing a barrier material with a thickness that allows for barrier property, but does not impose a large dimension to negatively influence the size or function of the electrode construction. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
11. (Original) The method of claim 9, wherein the first conductive layer is TiN, the second conductive layer is TaN, and the protective layer is TaN containing boron.
12. The method of claim 11, wherein the first conductive layer is TiN, the second conductive layer is TaN and the protective layer is TaN containing boron.
12. (Original) The method of claim 9, wherein the metallic layer includes a W layer formed by using a gas containing WF6.
15. The method of claim 11, wherein the metallic layer includes a W layer formed by using a gas containing WF.sub.6.
13. (Original) The method of claim 9, further comprising, after the metallic layer is formed, performing an annealing operation at a temperature from 450 °C to 650 °C.
16. The method of claim 11, further comprising, after the metallic layer is formed, performing an annealing operation at a temperature from 450° C. to 650° C.
14. (Original) The method of claim 11, further comprising, after forming the first conductive layer and before forming the second conductive layer:
forming a first cap layer over the first conductive layer;
performing an annealing operation after the first cap layer is formed; and removing the first cap layer after the annealing operation.
17. The method of claim 11, further comprising, after forming the first conductive layer and before forming the second conductive layer:
forming a first cap layer over the first conductive layer;
performing an annealing operation after the first cap layer is formed; and
removing the first cap layer after the annealing operation.
15. (Original) The method of claim 14, wherein the first cap layer is made of crystalline, polycrystalline or amorphous silicon.
18. The method of claim 17, wherein the first cap layer is made of crystalline, polycrystalline or amorphous silicon.
16. (Original) The method of claim 9, wherein:
forming the metallic layer includes applying the metal containing gas over the protective layer to form a nucleation layer, and forming a TiN layer over the nucleation layer, after the TiN layer is formed a second annealing operation is performed.
19. The method of claim 11,
wherein:
the forming a metallic layer includes applying the metal containing gas over the protective layer to form a nucleation layer, and forming a TiN layer over the nucleation layer, after the TiN layer is formed a second annealing operation is performed.
17. (Original) The method of claim 9, wherein: the protective layer is positioned between the metallic layer and the second conductive layer.
Established in claim 11, “forming a second conductive layer over the first conductive layer; forming a protective layer on a surface or at a surface region of the second conductive layer; forming a metallic layer by using a metal containing gas over the protective layer;”
18. (Original) A method of manufacturing a semiconductor device including a field effect transistor, comprising:
A forming a fin structure including a channel region;
B forming a gate dielectric layer over the channel region;
C forming a TiN layer over the gate dielectric layer;
D forming a TaN layer over the TiN layer;
E forming a protective layer over the TaN layer;
F forming a work function adjustment layer (this is Applicant’s layer 82 in Fig. 5D, ¶ 0053) over the protective layer; and
G forming a metal gate layer (this is Applicant’s layer 84 in Fig. 5D, ¶ 0052) over the work function adjustment layer,
H wherein the protective layer is resistive to a solution containing H3PO4.
11. A method of manufacturing a semiconductor device including a field effect transistor, comprising:
B forming a gate dielectric layer over a channel region;
C forming a first conductive layer over the gate dielectric layer;
D forming a second conductive layer over the first conductive layer;
E forming a protective layer on a surface or at a surface region of the second conductive layer;
F forming a metallic layer by using a metal containing gas over the protective layer; and
removing the metallic layer by a wet etching operation using a solution containing H.sub.3PO.sub.4,
wherein the protective layer protects the second conductive layer from the solution of the wet etching operation so that the protective layer remains at an end of the wet etching operation.
The ‘534 patent does not disclose instant application claim 18 features,
F “forming a work function adjustment layer (this is Applicant’s layer 82 in Fig. 5D, ¶ 0053) over the protective layer; and
G forming a metal gate layer (this is Applicant’s layer 84 in Fig. 5D, ¶ 0052) over the work function adjustment layer”, nor would it have been obvious as to a motivation as to modify the ‘534 patent in the manner claimed.
19. (Original) The method of claim 18, wherein: the protective layer is made of Ta containing N and B, and a thickness of the protective layer is in a range from 1 nm to 10 nm.
N/A
20. (Original) The method of claim 18, wherein the gate dielectric layer includes fluorine in an amount of 0.01 atomic% to 40 atomic%.
N/A
21. (New) A method of manufacturing a semiconductor device, comprising:
A forming a gate dielectric layer over a channel region;
B forming a first conductive layer over the gate dielectric layer;
C forming a cap layer over the first conductive layer;
C1 performing a laser annealing operation after the cap layer is formed;
C2 removing the cap layer after the laser annealing operation;
D forming a second conductive layer over the first conductive layer;
E forming a protective layer at a surface region of the second conductive layer E1 by implanting a dopant into the surface region of the second conductive layer,
E2 wherein the dopant is selected from the group consisting of boron, silicon, carbon, and nitrogen;
F forming a metallic layer by applying a metal containing gas on the protective layer; and
G removing the metallic layer by a wet etching operation using a solution.
11. A method of manufacturing a semiconductor device including a field effect transistor, comprising:
A forming a gate dielectric layer over a channel region;
B forming a first conductive layer over the gate dielectric layer;
D forming a second conductive layer over the first conductive layer;
E forming a protective layer on a surface or at a surface region of the second conductive layer;
F forming a metallic layer by using a metal containing gas over the protective layer; and
G removing the metallic layer by a wet etching operation using a solution containing H.sub.3PO.sub.4,
wherein the protective layer protects the second conductive layer from the solution of the wet etching operation so that the protective layer remains at an end of the wet etching operation.
17. The method of claim 11, further comprising, after forming the first conductive layer and before forming the second conductive layer:
C forming a first cap layer over the first conductive layer;
C1 (partial, because the laser aspect to be addressed below) performing an annealing operation after the first cap layer is formed; and
C2 removing the first cap layer after the annealing operation.
First, the ‘534 patent does not disclose, C1 “performing a laser annealing operation after the cap layer is formed;”, which is only that the anneal is carried out by laser.
Lee discloses in ¶ 0073, “Thereafter, an annealing process, e.g., a rapid thermal annealing (RTA) process, a spike RTA process, a flash RTA process, or a laser annealing process, may be performed on the gate electrode layer.”, where a gate annealing process is carried out by laser. The ‘534 reference already anneals the cap layer, just does not specify that the anneal is carried out by laser method.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “C1 performing a laser annealing operation after the cap layer is formed;”, as disclosed by Lee in the system of ‘534 patent, for the purpose of utilizing one of several methods to deliver targeted heat treatment to locations which require crystallization to perform as intended in the material state required for normal device function. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, the 534’ patent claims do not disclose wherein the dopants are introduced into the second conductive layer by implantation process. However, the second conductive layer is doped by gas application, see claim 13. So the type of dopant introduction process is merely lacking. Foord discloses in ¶ 0037, “The hardening process is not limited to beryllium ions and other ions can be used to provide a similar effect. For example, Li.sup.+, Mg.sup.+, and Ca.sup.+may be useful to implant into Si or other materials. Other material that may be useful for implanting to harden a material include Ga.sup.+, Xe.sup.+, Ar.sup.+, O.sup.+, In.sup.+, Si.sup.+, Kr.sup.+, and Bi.sup.+. Implanting may be useful to harden almost any material, but the process may be particularly useful in applications that harden silicon, silicon nitride, silicon carbide, tungsten, SiGe, low-k dielectric materials (“carbon-doped oxide”), tantalum, tantalum nitride, titanium, titanium nitride, aluminum.” This teaching shows the process of hardening material layers with implantation of ion species to modify the etch rate (see title) of the material films. One material film noted is “tantalum nitride” and one of the type of implantable dopant species is silicon.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the E1 “by implanting a dopant into the surface region of the second conductive layer”, as disclosed by Foord in the system of ‘534 patent, for the purpose of utilizing a method of doping which can accurately deliver dopants at the desired material layer depth and quantity. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
As the ‘534 patent already shows the other dopant species in claim 13, the only missing piece of E1 and E2, was the implantation process. See claim 13 which shows dopant species introduced by doping into the second conductive layer.
E1/E2 13. The method of claim 11, wherein the protective layer is formed by applying a gas containing one element selected from the group consisting of B, N, C, and Si to a surface of the second conductive layer.
22. (New) The method of claim 21, wherein: the second conductive layer is TaN, and the protective layer is TaN containing boron.
12. The method of claim 11, wherein the first conductive layer is TiN, the second conductive layer is TaN and the protective layer is TaN containing boron.
23. (New) The method of claim 21, wherein the metallic layer includes a W layer formed by a gas containing WF6.
15. The method of claim 11, wherein the metallic layer includes a W layer formed by using a gas containing WF.sub.6.
24. (New) The method of claim 21, wherein the protective layer includes Ta doped with one of B, Si, N or C; Ti doped with one of B, Si, C or N; a silicide, a polymer, or a dielectric.
12. The method of claim 11, wherein the first conductive layer is TiN, the second conductive layer is TaN and the protective layer is TaN containing boron.
25. (New) The method of claim 21, wherein the solution includes H3PO4.
This aspect taught in claim 11, portion, “wet etching operation using a solution containing H3PO4”
26. (New) The method of claim 21, wherein a loss of a thickness of the second conductive layer after the wet etching operation is less than 0.5 nm compared with a thickness of the second conductive layer as formed.
N/A. This feature in the ‘534 patent is applied to the “first conductive layer”, thus this limitation is not taught by the ‘534 patent, nor would it have been obvious as to a motivation as to modify the ‘534 patent in the manner claimed.
27. (New) The method of claim 21, wherein a thickness of the protective layer is in a range from 1 nm to 10 nm.
The ‘534 patent does not disclose the content of claim 27. However Ogawa discloses a tantalum nitride film for use as a barrier layer in a gate electrode is 1 nm in thickness, see ¶ 0028, “The second gate electrode 14B includes a second conductive film 32 made of tantalum nitride (TaN) having a thickness of 5 nm”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a thickness of the protective layer is in a range from 1 nm to 10 nm”, as disclosed by Ogawa in the system of ‘534 patent, for the purpose of utilizing a barrier material with a thickness that allows for barrier property, but does not impose a large dimension to negatively influence the size or function of the electrode construction. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
28. (New) The method of claim 21, wherein the gate dielectric layer includes fluorine in an amount of 0.01 atomic% to 40 atomic%.
The ‘534 patent does not disclose the content of claim 28. However Savant discloses the claim limitation in ¶ 0038, “The concentration of the fluorine in the gate dielectric layer 82 is in a range from about 0.01 atomic % to about 40 atomic %”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the gate dielectric layer includes fluorine in an amount of 0.01 atomic% to 40 atomic%.”, as disclosed by Savant in the system of ‘534 patent, for the purpose of decreasing defects, such as vacancies and dangling bonds in the gate dielectric layer, and improve device leakage issue and reliability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 18-20 are allowed.
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Regarding claim 18, the prior art of Wang et al. (US 9,418,853) discloses a multilayer gate electrode stack in Fig. 9, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed method steps which establish the claimed features of a fine structure, channel region, gate dielectric layer, TiN layer, TaN layer, protective layer, work function adjustment layer, metal gate layer, and the protective layer is resistive to H3PO4 solution, and their relative orientation to each other, in conjunction with the features of,
“forming a work function adjustment layer over the protective layer; and
forming a metal gate layer over the work function adjustment layer,”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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