DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/22/2024, 9/10/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3 and 5-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 5-6 of U.S. Patent No. 12,021,132 in view of Li (US 2019/0378913).
Regarding claim 1, Pat '132 discloses, in claims 1 and 3, a device, comprising:
a substrate; channel layers over the substrate; a gate dielectric layer around the channel layers; a first work function metal layer around the gate dielectric layer; a second work function metal layer over the first work function metal layer; a passivation layer between the first work function metal layer and the second work function metal layer, wherein the passivation layer merges in space vertically between adjacent ones of the channel layers (all limitations are the same with the limitations recited in claim 1 of Pat '132);
a blocking layer over the second work function metal layer; and a bulk metal layer over the blocking layer ("a blocking layer between the second work function metal layer and the bulk metal layer", in claim 3 of Pat '132, is interpreted as the same limitation).
Pat '132 does not explicitly disclose a composition of the blocking layer is the same as a composition of the passivation layer.
Li teaches, in at least figure 9 and related text, the device comprising a composition of the blocking layer (104, [42]) is the same as a composition of the passivation layer (100, [41]), for the purpose of providing finFETs utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices ([1]).
Pat '132 and Li are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '132 with the specified features of Li because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '132 to have the composition of the blocking layer being the same as a composition of the passivation layer, as taught by Li, for the purpose of providing finFETs utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices ([1], Li).
Regarding claim 2, Pat '132 in view of Li discloses the device of claim 1 as described above.
Pat '132 further discloses, in claim 1, the passivation layer comprises silicon, silicon dioxide, or alumina ("the passivation layer comprises silicon, silicon oxide, alumina, or a combination thereof", in claim 1 of Pat '132, is interpreted as the same limitation).
Regarding claim 3, Pat '132 in view of Li discloses the device of claim 1 as described above.
Li further teaches, in at least figure 9 and related text, the passivation layer (100, [41]) comprises a thickness between about 1 nm and about 2 nm, for the purpose of providing finFETs utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices ([1]).
Regarding claim 5, Pat '132 in view of Li discloses the device of claim 1 as described above.
Pat '132 further discloses, in claims 5 and 6, the first work function metal layer comprises an n-type work function metal layer ("the first work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiA1C and TiN", in claim 5 of Pat '132, is interpreted as the same limitation),
wherein the second work function metal layer comprises a p-type work function metal layer ("the second work function metal layer includes TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, or NiSi2", in claim 6 of Pat '132, is interpreted as the same limitation).
Regarding claim 6, Pat '132 in view of Li discloses the device of claim 1 as described above.
Pat '132 further discloses, in claim 5, the first work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiAlC and TiN (all limitations are the same with the limitations recited in claim 5 of Pat '132).
Regarding claim 7, Pat '132 in view of Li discloses the device of claim 1 as described above.
Pat '132 further discloses, in claim 6, the second work function metal layer includes TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, or NiSi2 (all limitations are the same with the limitations recited in claim 6 of Pat '132).
Regarding claim 8, Pat '132 in view of Li discloses the device of claim 1 as described above.
Li further teaches, in at least figure 9 and related text, a bulk metal layer (106, [42]) disposed over the blocking layer (104, [42]) such that the blocking layer (104, [42]) is sandwiched between the bulk metal layer (106, [42]) and the second work function metal layer (102, [41]), for the purpose of providing finFETs utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices ([1]).
Regarding claim 9, Pat '132 in view of Li discloses the device of claim 8 as described above.
Li further teaches, in at least figure 9 and related text, the bulk metal layer (106, [42]) comprises aluminum (Al) ([42]), tungsten (W) ([42]) or copper (Cu) ([42]), for the purpose of providing finFETs utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices ([1]).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of U.S. Patent No. 12,021,132 in view of Li (US 2019/0378913), and further in view of Chiang (US 2020/0411387).
Regarding claim 4, Pat '132 in view of Li discloses the device of claim 1 as described above.
Pat '132 in view of Li does not explicitly disclose the channel layers are disposed vertically one over another.
Chiang teaches, in at least figure 2I-2 and related text, the device comprising the channel layers (122, [43]) are disposed vertically one over another, for the purpose of preventing metal element diffusion from the NMG toward PFET due to the ultra-thin NWF layer and the blocking ability of the passivation layer in nanosheet GAA structures ([16]).
Pat '132, Li, and Chiang are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '132 in view of Li with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '132 in view of Li to have the channel layers being disposed vertically one over another, as taught by Chiang, for the purpose of preventing metal element diffusion from the NMG toward PFET due to the ultra-thin NWF layer and the blocking ability of the passivation layer in nanosheet GAA structures ([16], Chiang).
Claims 10-11 and 13-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 5-6 of U.S. Patent No. 12,021,132 in view of Chiang (US 2020/0411387).
Regarding claim 10, Pat '132 discloses, in claims 1, 3 and 5-6, a semiconductor device, comprising:
a substrate (all limitations are the same with the limitations recited in claim 1 of Pat '132);
an n-type work function metal layer around the gate dielectric layer (“a first work function metal layer around the gate dielectric layer” and "the first work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiA1C and TiN", in claims 1 and 5 of Pat '132, are interpreted as the same limitation);
a p-type work function metal layer over the n-type work function metal layer (“a second work function metal layer over the first work function metal layer” and "the second work function metal layer includes TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, or NiSi2", in claims 1 and 6 of Pat '132, are interpreted as the same limitation); a passivation layer between the n-type work function metal layer and the p-type work function metal layer (“a passivation layer between the first work function metal layer and the second work function metal layer", in claim 1 of Pat '132, is interpreted as the same limitation);
a blocking layer over the p-type work metal layer; and a bulk metal layer over the blocking layer (“a blocking layer between the second work function metal layer and the bulk metal layer", in claim 3 of Pat '132, is interpreted as the same limitation),
wherein the passivation layer merges in space vertically between adjacent ones of the plurality of channel members to prevent the p-type work function metal layer from extending into the space (“the passivation layer merges in space vertically between adjacent ones of the channel layers", in claim 1 of Pat '132, is interpreted as the same limitation).
Pat '132 does not explicitly disclose a base fin extending from the substrate; a plurality of channel members disposed over the base fin; a gate dielectric layer wrapping around each of the plurality of channel members.
Chiang teaches, in at least figure 2I-2 and related text, the device comprising a base fin (102F, [22]) extending from the substrate (102, [22]); a plurality of channel members (122, [43]) disposed over the base fin (102F, [22]); a gate dielectric layer (142, [39]) wrapping around each of the plurality of channel members (122, [43]), for the purpose of preventing metal element diffusion from the NMG toward PFET due to the ultra-thin NWF layer and the blocking ability of the passivation layer in nanosheet GAA structures ([16]).
Pat '132 and Chiang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '132 with the specified features of Chiang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '132 to have the base fin extending from the substrate; the plurality of channel members disposed over the base fin; the gate dielectric layer wrapping around each of the plurality of channel members, as taught by Chiang, for the purpose of preventing metal element diffusion from the NMG toward PFET due to the ultra-thin NWF layer and the blocking ability of the passivation layer in nanosheet GAA structures ([16], Chiang).
Regarding claim 11, Pat '132 in view of Chiang discloses the semiconductor device of claim 10 as described above.
Pat '132 further discloses, in claim 1, the passivation layer comprises silicon, silicon dioxide, or alumina ("the passivation layer comprises silicon, silicon oxide, alumina, or a combination thereof", in claim 1 of Pat '132, is interpreted as the same limitation).
Regarding claim 13, Pat '132 in view of Chiang discloses the semiconductor device of claim 10 as described above.
Pat '132 further discloses, in claim 5, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiAlC and TiN (“the first work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiAlC and TiN ", in claim 5 of Pat '132, is interpreted as the same limitation).
Regarding claim 14, Pat '132 in view of Chiang discloses the semiconductor device of claim 10 as described above.
Pat '132 further discloses, in claim 6, the p-type work function metal layer includes TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, or NiSi2 (“the second work function metal layer includes TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, or NiSi2", in claim 6 of Pat '132, is interpreted as the same limitation).
Regarding claim 15, Pat '132 in view of Chiang discloses the semiconductor device of claim 10 as described above.
Pat '132 in view of Chiang does not explicitly disclose the passivation layer comprises a thickness between about 1 nm and about 2 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the thickness of the passivation layer as claimed in claim 15 in order to optimize the performance of the device in .. It is noted that the selection dimension of the thickness of the passivation layer as being no more than use of known technique to improve similar devices in the same way. See MPEP 2143 I. C. It is noted that if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill. KSR International Co. v. Teleflex Inc., 550 US 398, 82 USPQ2d 1385, 1389 (2007). In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The specification contains no disclosure of either the critical nature of the claimed arrangement (i.e.- the passivation layer comprises a thickness between about 1 nm and about 2 nm) or any unexpected results arising therefrom.
Where patentability is said to be based upon particular chosen limitations or upon another variable recited in a claim, the applicant must show that the chosen limitations are critical. In re Woodruff, 919 F.2d 1575, 1578 (FED. Cir. 1990).
Regarding claim 16, Pat '132 in view of Chiang discloses the semiconductor device of claim 10 as described above.
Chiang further teaches, in at least figure 2I-2 and related text, the gate dielectric layer (142, [39]) comprises a thickness between about 1 nm and about 2 nm, for the purpose of preventing metal element diffusion from the NMG toward PFET due to the ultra-thin NWF layer and the blocking ability of the passivation layer in nanosheet GAA structures ([16]).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 10 and 12 that recite "the blocking layer comprises silicon, silicon dioxide, or alumina" in combination with other elements of the base claims 10 and 12.
Claims 17-20 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 that recite "the passivation layer and the block layer comprise silicon, silicon dioxide, or alumina" in combination with other elements of the base claims 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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