DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/22/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,027,372. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 12,027,372 recites all of the limitations in claim 1 of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,027,372. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 12,027,372 recites all of the limitations in claim 2 of the instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,027,372. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 3 of U.S. Patent No. 12,027,372 recites all of the limitations in claim 3 of the instant application.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,027,372. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 6 of U.S. Patent No. 12,027,372 recites all of the limitations in claim 4 of the instant application.
Prior art of record
Re claim 1, Li et al. (2014/0206190) teaches a method (Figs. 1-8), comprising: epitaxially growing [20, 32] a doped region (108) on a substrate (102); forming a metal-rich conductive layer (402) in the doped region (108); forming a metal layer (502) on a semiconductor-rich conductive layer (404).
Li does not explicitly teach forming a semiconductor-rich conductive layer on the metal-rich conductive layer.
Re claim 11, Li et al. (2014/0206190) teaches a method (Figs. 1-8), comprising: epitaxially growing [20, 32] a doped region (108) on a substrate (102); forming a first metal silicide layer [25] in the doped region (108), wherein a concentration of metal atoms in the first metal silicide layer is greater than a concentration of silicon atoms in the first metal silicide layer [23-25]. Li does not explicitly teach forming a second metal silicide layer on the first metal silicide layer, wherein a concentration of silicon atoms in the second metal silicide layer is greater than a concentration of metal atoms in the second metal silicide layer; and forming a metal layer on the second metal silicide layer.
Re claim 17, Li et al. (2014/0206190) teaches a semiconductor device (Figs. 1-8), comprising: a substrate (102); a gate structure (104) disposed on the substrate (102); a doped region (108) disposed adjacent to the gate structure (104); and a conductive structure (Fig. 8), comprising: a first metal silicide layer [25] disposed in the doped region (108), wherein a concentration of metal atoms in the first metal silicide layer is greater than a concentration of silicon atoms in the first metal silicide layer [23-25]; Li does not explicitly teach a second metal silicide layer disposed on the first metal silicide layer, wherein a concentration of silicon atoms in the second metal silicide layer is greater than a concentration of metal atoms in the second metal silicide layer; a third metal silicide layer disposed on the second metal silicide layer; and a metal layer disposed on the third metal silicide layer.
Allowable Subject Matter
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the method of claim 1, including each of the limitations and specifically forming a semiconductor-rich conductive layer on the metal-rich conductive layer, for the same reasons as mentioned for claim 1 in the prior art of record above. The prior art of record does not anticipate or make obvious the method of claim 11, including each of the limitations and specifically forming a second metal silicide layer on the first metal silicide layer, wherein a concentration of silicon atoms in the second metal silicide layer is greater than a concentration of metal atoms in the second metal silicide layer; and forming a metal layer on the second metal silicide layer, for the same reasons as mentioned for claim 11 in the prior art of record above.
The prior art of record does not anticipate or make obvious the device of claim 17, including each of the limitations and specifically a second metal silicide layer disposed on the first metal silicide layer, wherein a concentration of silicon atoms in the second metal silicide layer is greater than a concentration of metal atoms in the second metal silicide layer; a third metal silicide layer disposed on the second metal silicide layer; and a metal layer disposed on the third metal silicide layer, for the same reasons as mentioned for claim 17 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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