DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Amendment filed on 01/14/2026 has been received and entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- 4, 6, 9-14, 16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martin (EP-3945521-A1).
Regarding claim 1, Martin (Fig. 3) shows a computing circuit, comprising:
a first magnetic tunnel junction (11), configured to store a first logic value based on a write current; and
a second magnetic tunnel junction (10), configured to store a second logic value based on the write current,
wherein the first logic value (parallel state) is different from the second logic value, (anti-parallel state) and
the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel (10 is parallel to 11).
Regarding claim 11, Martin discloses a memory cell (100), comprising:
a storage circuit, configured to store data (0 or 1); and
a computing circuit, configured to perform a calculation based on the data and comprising:
a first magnetic tunnel junction, configured to store a first logic value based on a write current; and
a second magnetic tunnel junction, configured to store a second logic value based on the write current, wherein the first logic value is different from the second logic value], and
the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel (see the rejection of claim 1).
Regarding claim 18, Martin discloses (see the rejections of claims 1 and 11) a compute-in-memory device, comprising:
a memory array, comprising:
a plurality of memory cells, wherein each of the memory cell comprises:
a storage circuit, configured to store data; and
a computing circuit, configured to perform a calculation based on the data and comprising:
a first magnetic tunnel junction, configured to store a first logic value based on a write current; and
a second magnetic tunnel junction, configured to store a second logic value based on the write current,
wherein the first logic value is different from the second logic value and the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in parallel;
a plurality of word lines, respectively coupled to a row of the plurality of memory cells; and
a plurality of bit lines, respectively coupled to a column of the plurality of memory cells;
a bit line decoder, configured to select voltage signals from the plurality of bit lines according to a first address signal; and
a word line decoder, configured to select the plurality of word lines according to a second address signal.
It is inherent that the MRAM cells are arranged in rows and columns to form an array and the MRAM device has a bit line decoder and a word line decoder.
Regarding claims 2, 12 and 19, Martin discloses the computing circuit according to claim 1, the memory cell of claim 11 and the compute-in-memory of claim 18, wherein each of the first magnetic tunnel junction and the second magnetic tunnel junction is a spin-orbit torque magnetic random-access memory cell (In particular, the present invention concerns a MRAM cell that can be written using a spin orbit torque (SOT) interaction and a magnetic memory having a high density of MRAM cell.).
Regarding claims 3, 13 and 20, Martin (Fig. 1), Fig. 4 and Fig. 5) shows the computing circuit according to claim 1, the memory cell of claim 11 and the compute-in-memory of claim 18, wherein
the second magnetic tunnel junction is disposed as a mirror image of the first magnetic tunnel junction across a mirror axis (the vertical axis in the middle of 10 and 11).
Regarding claims 4 and 14, Martin discloses the computing circuit according to claim 1 and the memory cell of claim 11, wherein
a first magnetic polarity of the first magnetic tunnel junction caused by the write current is different from a second magnetic polarity of the second magnetic tunnel junction caused by the write current (Due to the U-shape configuration, a write current 31 flows in the write current line 30 with opposed polarity relative to the first magnetization 210 of the first and second MTJ elements 10, 11.).
5. (Original) The computing circuit according to claim 1, wherein a first disposing angle of the first magnetic tunnel junction is different from a second disposing angle of the second magnetic tunnel junction.
Regarding claims 6 and 16, Martin (Fig. 3) shows the computing circuit according to claim 1 and the memory cell of claim 11, wherein
a first current direction of the write current flowing in a spin-orbit torque line of the first magnetic tunnel junction is different from a second current direction of the write current flowing in a spin-orbit torque line of the second magnetic tunnel junction (a write current 31 flows in the write current line 30 with opposed polarity relative to the first magnetization 210 of the first and second MTJ elements 10, 11).
Regarding claim 9, Martin (Fig. 3) discloses the computing circuit according to claim 1, wherein
each of the first magnetic tunnel junction and the second magnetic tunnel junction comprises:
a reference layer, wherein a magnetic polarity of the reference layer is fixed based on the write current; and
a free layer, wherein a magnetic polarity of the free layer changes based on the write current.
Regarding claim 10, Martin (Fig. 3) shows the computing circuit according to claim 9, wherein
the first logic value is represented by a magnetic polarity of the reference layer being parallel to a magnetic polarity of the free layer; and
the second logic value is represented by the magnetic polarity of the reference layer being antiparallel to the magnetic polarity of the free layer.
Regarding claim 12, Martin discloses the memory cell according to claim 11, wherein each of the first magnetic tunnel junction and the second magnetic tunnel junction is a spin-orbit torque magnetic random-access memory cell (see the rejection of claim 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Martin.
Claims 5 and 15 differ from Martin in reciting that a first disposing angle of the first magnetic tunnel junction is different from a second disposing angle of the second magnetic tunnel junction. It would have been a matter of design choice to use the first disposing angle of the first magnetic tunnel junction different from a second disposing angle of the second magnetic tunnel junction since Applicant has stated that the value of the first disposing angle and the second disposing angle may be determined according to design needs (paragraph [0024], page 6, lines 21-22) and it appears that the memory device would perform well with the first and second disposing angles of Martin.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Martin in view of Wang et al. (US 2020/0279597 cited in the previous office action, hereinafter "Wang").
The only difference between claims 7 and 17 and Martin is that the computing circuit is configured to perform a XOR calculation or a XNOR calculation of a first input signal and a second input signal. However, Wang discloses the use of a computational random access memory to perform a 2-input XOR calculation (Fig. 18a). It would have been obvious to one having ordinary skill in the art before the effective filing date of the
claimed invention to modify Martin by using use of a computational random access
memory to perform a 2-input XOR calculation in a magnetic memory device.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-7 and 9-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUAN HOANG/Primary Examiner, Art Unit 2827