DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The specification is objected because of the following reasons:
In par. [0001]: insert US Patent no. 12022644.
Appropriate correction is required.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,022,644 (Application 18/065,770); 11,569,247 (Application 17/227,592) & 10,978,460 (Application 16/383,957) and/or in view of Lee et al. (US 2019/0013354, Fig. 5). Although the claims at issue are not identical, they are not patentably distinct from each other because they require similar limitation such a memory cell with latch circuit, pass-gate transistor having first source/drain region, bit line, logic cell with transistor, second source/drain region, vias, contacts, local interconnection line, etc., and Lee’s Fig. 5 teaches the use of etching stop layer(s) & isolation layer(s).
Current Application 18/672,076
1. A semiconductor structure, comprising: a memory cell formed over a semiconductor substrate, comprising: a latch circuit formed by two cross-coupled inverters; a pass-gate transistor coupling an output of the latch circuit to a bit line; and a first etching stop layer formed on the bit line, wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact; and a logic cell, comprising: a transistor over the semiconductor substrate, wherein a second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact; and a second etching stop layer formed on the local interconnect line, wherein a first bottom surface of the bit line and a second bottom surface of the local interconnect line are coplanar, wherein a third bottom surface of the first etching stop layer is in contact with a first top surface of the bit line, and a fourth bottom surface of the second etching stop layer is in contact with a second top surface of the local interconnect line, and wherein the third bottom surface is higher than the fourth bottom surface.
US Patent No. 12,022,644
1. A semiconductor structure, comprising: a memory cell formed over a semiconductor substrate, comprising: a latch circuit formed by two cross-coupled inverters; and a pass-gate transistor coupling an output of the latch circuit to a bit line, wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact; and a logic cell, comprising: a transistor over the semiconductor substrate, wherein a second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact, wherein the local interconnect line and the bit line are formed in the same metal layer, and a top surface of the local interconnection line is lower than a top surface of the bit line.
11,569,247
1. A semiconductor structure, comprising: a memory cell formed over a semiconductor substrate, comprising: a latch circuit formed by two cross-coupled inverters; and a pass-gate transistor coupling an output of the latch circuit to a bit line, wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact; and a logic cell, comprising: a transistor over the semiconductor substrate, wherein a second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact, wherein height of the second via is greater than height of the first via, wherein the local interconnect line and the bit line are formed in the same metal layer, and the bit line is thicker than the local interconnect line.
10,978,460
1. A semiconductor structure, comprising: a memory cell formed over a semiconductor substrate, comprising: a latch circuit formed by two cross-coupled inverters; and a pass-gate transistor coupling an output of the latch circuit to a bit line, wherein a first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact; and a logic cell formed over the semiconductor substrate, comprising: a transistor over the semiconductor substrate, wherein a second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact, wherein the first via and the second via are the same height, wherein the local interconnect line of the logic cell and the bit line of the memory cell are formed in the same metal layer, and the bit line is thicker than the local interconnect line.
Allowable Subject Matter
3. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action.
The allowable subject matter includes “a memory cell…pass-gate transistor…and a first via over the first contact…wherein a second source/drain region…higher than the fourth bottom surface” (claim 1); “a memory cell…pass-gate transistor…and a first via over the first contact…wherein a second source/drain region…thicker than the local interconnection line formed in the second isolation layer” (claim 8); and “a memory cell…pass-gate transistor…and a first via over and contact with the first contact…wherein a second source/drain region…the local interconnect line…to a top surface of the second isolation layer” (claim 14).
The closest prior arts include Lee et al. (US 2019/0013354, directed to damascene based approach for embedding MTJ device in cell region, Fig. 5); Chen et al. (US 2017/0221905, directed to SRAM cell and logic cell design, Figs. 1 & 3), Liaw (US 2013/0181297, directed to SRAM cells and arrays, Fig. 3A), Morimoto et al. (US 2013/0026580, directed to semiconductor device, Fig. 9), Liaw (US 9,424,889, directed to multiple post SRAM device, Fig. 6), Hirose (US 2017/0317065, directed to semiconductor integrated circuit device, Fig. 2), Liaw (US 9,704,564, directed to SRAM structure, Fig. 3), Funane et al. (US 7,940,542, directed to semiconductor device having multiport memory, Fig. 13A), and Lee et al. (US 2004/0183101, directed to semiconductor device with bit line direct connected landing pad or concentration region, Figs. 1 & 8) individually or in combination with the prior arts of record, do not meet all the claimed features cited above.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/26/26
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