Prosecution Insights
Last updated: July 17, 2026
Application No. 18/672,485

LOW-STRESS PASSIVATION LAYER

Non-Final OA §102
Filed
May 23, 2024
Priority
Oct 18, 2019 — divisional of 11/031,325 +2 more
Examiner
OH, JAEHWAN
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 669 resolved
+24.9% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
18 currently pending
Career history
687
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
68.3%
+28.3% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 669 resolved cases

Office Action

§102
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (U.S. Patent Application Publication 2018/0040585, hereinafter referred to as Yu). As to claim 1, Yu teaches 1. A semiconductor structure, comprising: a first conductive feature; a second conductive feature disposed alongside the first conductive feature; a dielectric feature disposed between the first conductive feature and the second conductive feature; a polymeric layer disposed over the first conductive feature, the second conductive feature, and the dielectric feature; a first contact feature extending through the polymeric layer to contact a top surface of the first conductive feature; and a second contact feature extending through the polymeric layer to contact a top surface of the second conductive feature, wherein a top portion of the dielectric feature is disposed between the first contact feature and the second contact feature along a direction. [see 170, 120, 32, 38, 40 in Fig. 8 for example] As to claim 2, Yu teaches 2. The semiconductor structure of claim 1, wherein each of the first contact feature and the second contact feature is spaced apart from the top portion of the dielectric feature by a portion of the polymeric layer. [see 38 in Fig. 8 for example] As to claim 3, Yu teaches 3. The semiconductor structure of claim 1, wherein the polymeric layer comprises a photoresist material, a polymeric material, polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). [¶0032] As to claim 4, Yu teaches 4. The semiconductor structure of claim 1, wherein the first contact feature comprises: a seed layer in contact with a top surface of the first conductive feature and the polymeric layer; and a conductive pillar over the seed layer and spaced apart from the top surface of the first conductive feature and the polymeric layer by the seed layer. [¶0036] As to claim 5, Yu teaches 5. The semiconductor structure of claim 4, wherein the seed layer comprises copper (Cu), tantalum (Ta), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN). [¶0036] As to claim 6, Yu teaches 6. The semiconductor structure of claim 4, wherein the conductive pillar comprises copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, or an alloy thereof. [¶0036] As to claim 7, Yu teaches 7. The semiconductor structure of claim 4, wherein the first contact feature further comprises a solder feature disposed over the conductive pillar. [¶0037] As to claim 8, Yu teaches 8. The semiconductor structure of claim 7, wherein the solder feature comprises Pb-Sn, InSb, tin, silver, copper, or a combination thereof. [¶0037] As to claim 9, Yu teaches 9. The semiconductor structure of claim 1, wherein the dielectric feature comprises: at least two oxygen-containing dielectric layers; and a nitrogen-containing dielectric layer over the at least two oxygen-containing dielectric layer. [¶0012] As to claim 10, Yu teaches 10. The semiconductor structure of claim 9, wherein the at least two oxygen-containing dielectric layers comprise silicon oxide, wherein the nitrogen-containing dielectric layer comprises silicon nitride or silicon carbonitride. [¶0012] As to claim 11, Yu teaches 11. A semiconductor structure, comprising: a first conductive feature; a second conductive feature disposed alongside the first conductive feature; a first contact feature extending toward a top surface of the first conductive feature; a second contact feature extending toward a top surface of the second conductive feature; and a dielectric feature disposed between the first conductive feature and the second conductive feature as well as between the first contact feature and the second contact feature, wherein the dielectric feature comprises: at least two oxygen-containing dielectric layers; and a nitrogen-containing dielectric layer over the at least two oxygen-containing dielectric layer. [see 170, 120, 32, 38, 40 in Fig. 8 for example] As to claim 12, Yu teaches 12. The semiconductor structure of claim 11, wherein sidewalls of the first contact feature and the second contact feature are spaced apart from sidewalls of the dielectric feature by a polymeric layer. [see 170, 120, 32, 38, 40 in Fig. 8 for example] As to claim 13, Yu teaches 13. The semiconductor structure of claim 12, wherein the polymeric layer extends continuously over a top surface of the dielectric feature. [see 32 in Fig. 8 for example] As to claim 14, Yu teaches 14. The semiconductor structure of claim 12, wherein the polymeric layer comprises a photoresist material, a polymeric material, polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). [¶0032] As to claim 15, Yu teaches 15. The semiconductor structure of claim 12, wherein the first contact feature comprises: a seed layer in contact with a top surface of the first conductive feature and the polymeric layer; and a conductive pillar over the seed layer and spaced apart from the top surface of the first conductive feature and the polymeric layer by the seed layer. [¶0036] As to claim 16, Yu teaches 16. The semiconductor structure of claim 15, wherein the seed layer comprises copper (Cu), tantalum (Ta), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN). [¶0036] As to claim 17, Yu teaches 17. The semiconductor structure of claim 15, wherein the conductive pillar comprises copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, or an alloy thereof. [¶0036] As to claim 18, Yu teaches 18. A semiconductor structure, comprising: a first conductive feature; a second conductive feature disposed alongside the first conductive feature; a dielectric feature disposed between the first conductive feature and the second conductive feature; a polymeric layer disposed over the first conductive feature, the second conductive feature, and the dielectric feature; a first contact feature extending through the polymeric layer to contact a top surface of the first conductive feature; and a second contact feature extending through the polymeric layer to contact a top surface of the second conductive feature, wherein a top portion of the dielectric feature extends between the first contact feature and the second contact feature along a direction, wherein each of the first contact feature and the second contact feature is spaced apart from the top portion of the dielectric feature by a portion of the polymeric layer; wherein the first contact feature comprises: a seed layer in contact with a top surface of the first conductive feature and the polymeric layer, and a conductive pillar over the seed layer and spaced apart from the top surface of the first conductive feature and the polymeric layer by the seed layer. [see 170, 120, 32, 38, 40 in Fig. 8 for example] As to claim 19, Yu teaches 19. The semiconductor structure of claim 18, wherein the seed layer comprises copper (Cu), tantalum (Ta), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), wherein the conductive pillar comprises copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, or an alloy thereof. [see 38 in Fig. 8 for example] As to claim 20, Yu teaches 20. The semiconductor structure of claim 18, wherein the first contact feature further comprises a solder feature disposed over the conductive pillar. [see 40 in Fig. 8 for example] Conclusion Claims 1-20 are rejected as explained above. The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAEHWAN OH/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

May 23, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 669 resolved cases by this examiner. Grant probability derived from career allowance rate.

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