DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device in the reply filed on 12 August 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hui Zang et al. (US 20180047734 A1; hereinafter Zang).
Regarding Claim 1, Zang discloses a semiconductor device (Fig. 6), comprising:
a substrate (102; ¶0025);
a fin grid (comprising horizontal fins 137 and vertical fins 139; ¶0035), extending above the substrate (102), comprising:
a first plurality of semiconductor fin structures (137; ¶0034-0035) extending in a first direction (horizontal) and arranged in a second direction (vertical); and
a second plurality of semiconductor fin structures (139; ¶0034-0035) extending in the second direction (vertical) and arranged in the first direction (horizontal),
wherein the first plurality of semiconductor fin structures (137) intersect the second plurality of semiconductor fin structures (139) at a plurality of intersection points (as shown in Fig. 6);
a first plurality of gate structures (plurality of 135; ¶0035) on the first plurality of semiconductor fin structures (137); and
a second plurality of gate structures (135 and 142; ¶0035) on the second plurality of semiconductor fin structures (139) (as shown in Fig. 6).
Zang does not expressly disclose the cross fin device (of Fig. 6) extends above the substrate (102), as the substrate is not shown in the figure.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cross fin structure of Zang’s Fig. 6 extend above the substrate (described in ¶0024-0026) to employ conventional fabrication techniques to make the device (Zang; ¶0024-0026).
Regarding Claim 6, Zang teaches the semiconductor device of claim 1, but does not expressly disclose it further comprising: a first plurality of gate contacts on the first plurality of gate structures; and a second plurality of gate contacts on the second plurality of gate structures.
However, Zang discloses (¶0033) that the array may be connected using additional contacts and metal interconnections (not shown) as known to those skilled in the art. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a plurality of contacts on the plurality of first and second gate structures to provide electrical interconnections in a BEOL process to make a functional device (¶0033).
Regarding Claim 7, Zang teaches the semiconductor device of claim 1, further comprising:
first source/drain regions (131/133 respectively; ¶0035) at opposing ends of each of the first plurality of semiconductor fin structures (137); and
second source/drain regions (140/141 respectively which repeat along the length of the fin) at opposing ends of each of the second plurality of semiconductor fin structures (139) (as shown in Fig. 6).
Regarding Claim 8, Zang teaches the semiconductor device of claim 7, but does not expressly disclose further comprising:
first source/drain contacts on the first source/drain regions (131/133); and
second source/drain contacts on the second source/drain regions (140/141).
However, Zang discloses (¶0033) that the array may be connected using additional contacts and metal interconnections (not shown) as known to those skilled in the art.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a plurality of contacts on the plurality of first and second source/drain regions to provide electrical interconnections in a BEOL process to make a functional device (¶0033).
Claim(s) 21, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of Thomas Alava et al. (US 20200258783 A1; hereinafter Alava).
Regarding Claim 21, Zang discloses a semiconductor device (Fig. 9), comprising:
a semiconductor substrate (102; ¶0024-¶0025);
a first plurality of semiconductor fin structures (146; ¶0040) above the semiconductor substrate (102),
wherein the first plurality of semiconductor fin structures (146) extend in a first direction (up/down) and are arranged in a second direction (left/right) approximately perpendicular to the first direction (¶0040);
a second plurality of semiconductor fin structures (148; ¶0040) above the semiconductor substrate (102),
wherein the second plurality of semiconductor fin structures (148) extend in the second direction (left/right) and are arranged in the first direction (up/down),
wherein the first plurality of fins (146) are used for conventional FinFETs and the other set of fins (148) are used for a cross-fin structure (such as what is in Fig. 2; ¶0027).
Zang does not explicitly disclose wherein a second plurality of gate structures are on the second plurality of semiconductor fin structures (148) such that the second plurality of gate structures wrap around at least three sides of the second plurality of semiconductor fin structures (148), wherein the fin structures are above the semiconductor substrate.
However, Zang discloses in ¶0040 that the fin structures 148 may include the cross fin structure (such as what is in Fig. 2), which includes a plurality of gates (one gate 110 for at least each horizontal fin; ¶0027) that wraps around at least three sides of the fin (as shown in Fig. 2) that extends above a semiconductor substrate (102; ¶0025).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cross fin structure and gates of Zang’s device of Fig. 2 on the fins (148) of Zang’s Fig. 9 because Zang discloses it is so (in ¶0040) and/or in order to integrate a cross fin structure with a plurality of conventional FinFETs.
Zang does not expressly disclose the details of the conventional FinFETs on the fins (146), including a first plurality of gate structures on the first plurality of semiconductor fin structures (146) such that the first plurality of gate structures wrap around at least three sides of the first plurality of semiconductor fin structures (146). Zang describes the transistors on these fins as conventional FinFETs.
In the same field of endeavor, Alava discloses a FinFET (Fig. 4; ¶0050) including a gate structure (16/18; ¶0100) on a fin (7a; ¶0100), wherein the gate structure wraps around at least three sides of the fin (as shown in Fig. 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the example FinFET (and features thereof) of Alava for the FinFETs of fins 146 of Zang as an obvious example of a conventional FinFET and/or to provide a FinFET with a fin with reduced dimensions (Alava; ¶0050).
Regarding Claim 24, modified Zang teaches the semiconductor device of claim 21, wherein each of the first plurality of gate structures (Alava; 16/18) and each of the second plurality of gate structures (Zang, 110) comprises:
a gate dielectric layer (Alava; 16; ¶0092) on a semiconductor fin structure (7a) of the first plurality of semiconductor fin structures or on a semiconductor fin structure of the second plurality of semiconductor fin structures; and
a gate electrode layer (Alava; 18; ¶0092) on the gate dielectric layer (16).
Zang does not expressly disclose wherein each of the plurality of second gate structures (110) comprises a gate dielectric layer on a second semiconductor fin structure of the second plurality of semiconductor fin structures; and a gate electrode layer on the gate dielectric layer. Zang’s device is described as a field effect transistor (¶0001).
Alava discloses a field effect transistor comprises a gate dielectric (16) with a gate electrode (18) (as shown above). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the gate features of Alava for the gate of Zang to provide a field effect transistor (as intended) without shorting the gate to the channel (fin).
Regarding Claim 25, modified Zang teaches the semiconductor device of claim 21, but does not expressly disclose further comprising:
a first plurality of gate contacts on the first plurality of gate structures; and
a second plurality of gate contacts on the second plurality of gate structures.
However, Zang discloses (¶0033) that the devices may be connected using additional contacts and metal interconnections (not shown) as known to those skilled in the art. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a plurality of contacts on the plurality of first and second gate structures to provide electrical interconnections in a BEOL process to make a functional device (¶0033).
Claims 21, 22, 23, and 27 are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of Thomas Alava et al. (US 20200258783 A1; hereinafter Alava).
Regarding Claim 21, Zang discloses a semiconductor device (Fig. 6), comprising:
a semiconductor substrate (102; ¶0025);
a first plurality of semiconductor fin structures (139; ¶0035) above the semiconductor substrate (102),
wherein the first plurality of semiconductor fin structures (139) extend in a first direction (up/down) and are arranged in a second direction (left/right) approximately perpendicular to the first direction;
a second plurality of semiconductor fin structures (137; ¶0035) above the semiconductor substrate (102),
wherein the second plurality of semiconductor fin structures (137) extend in the second direction (left/right) and are arranged in the first direction (up/down);
a first plurality of gate structures (135, 142; ¶0035) on the first plurality of semiconductor fin structures (139); and
a second plurality of gate structures (plurality of 135) on the second plurality of semiconductor fin structures (on each of 137).
Zang does not expressly disclose wherein the first plurality of gate structures and the second plurality of gate structures wrap around at least three sides of their respective plurality of semiconductor fin structures.
In the same field of endeavor, Alava discloses a FinFET (Fig. 4; ¶0050) including a gate structure (16/18; ¶0100) on the fin (7a; ¶0100), wherein the gate structure wraps around at least three sides of the fin (as shown in Fig. 4).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the example FinFET (and features thereof) of Alava for the gates on the respective fins of Zang in order to provide improved channel control in the device.
Zang does not expressly disclose the cross fin device (of Fig. 6) that extends above the substrate (102), as the substrate is not shown in the figure.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the cross fin structure of Zang’s Fig. 6 extend above the substrate (described in ¶0024-0026) to employ conventional fabrication techniques to make the device (Zang; ¶0024-0026).
Regarding Claim 22, modified Zang teaches the semiconductor device of claim 21, further comprising:
first source/drain regions (131/133 respectively; ¶0035) at opposing ends of each of the first plurality of semiconductor fin structures (137); and
second source/drain regions (140/141 respectively which repeat along the length of the fin) at opposing ends of each of the second plurality of semiconductor fin structures (139) (as shown in Fig. 6).
Regarding Claim 23, modified Zang teaches the semiconductor device of claim 22, but does not expressly disclose further comprising:
a first plurality of source/drain contacts on the first source/drain regions (131/133); and
a second plurality of source/drain contacts on the second source/drain regions (140/141).
However, Zang discloses (¶0033) that the array may be connected using additional contacts and metal interconnections (not shown) as known to those skilled in the art. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have a plurality of contacts on the plurality of first and second source/drain regions to provide electrical interconnections in a BEOL process to make a functional device (¶0033).
Regarding Claim 27, modified Zang teaches the semiconductor device of claim 21, wherein two or more gate structures (135, 142), of the first plurality of gate structures, is located on a same semiconductor fin structure (one 139) of the first plurality of semiconductor fin structures (Fig. 6).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 17, the closest prior art (Michele Aldeghi et al. US 20240423102 A1; Fig. 2A) and (Shota Iizuka et al. US 20230200261 A1; Fig. 23) disclose various quantum computing devices comprising row and column configurations of quantum dots/qubits.
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); including (in their entirety):
A quantum computing semiconductor device comprising: a first plurality of semiconductor fin structures above the substrate,
wherein the first plurality of semiconductor fin structures extend in a first direction and are arranged in a second direction;
a second plurality of semiconductor fin structures above the substrate,
wherein the second plurality of semiconductor fin structures extend in the second direction and are arranged in the first direction;
a plurality of qubit regions at intersection points between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures;
a first plurality of barrier gate structures on the first plurality of semiconductor fin structures;
a second plurality of barrier gate structures on the second plurality of semiconductor fin structures; and
a plurality of plunger contacts on the plurality of qubit regions.
For at least this reason, claims 18-20 are also allowed based on their dependency from claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2-5, 26, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record teaches the device of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein two or more gate structures, of the first plurality of gate structures, is located on a same semiconductor fin structure of the first plurality of semiconductor fin structures; and
wherein each gate structure of the two or more gate structures is located between adjacent intersection points, of the plurality of intersection points, in the first direction.
For at least this reason, claims 3-4 would also be allowable based on their dependency from claim 2.
Regarding Claim 5, the prior art of record teaches the device of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
the semiconductor device of claim 1, further comprising: plunger contacts above the intersection points between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures.
Regarding Claim 26, the prior art teaches the semiconductor device of claim 21. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
a contact on each of a plurality of intersection points between the first plurality of semiconductor fin structures and the second plurality of semiconductor fin structures.
Regarding Claim 28, modified Zang teaches the device of claim 27. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
wherein another two or more gate structures, of the second plurality of gate structures, is located on a same semiconductor fin structure of the second plurality of semiconductor fin structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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